[v7,38/42] target/arm: Set PSTATE.TCO on exception entry

Message ID 20200603011317.473934-39-richard.henderson@linaro.org
State Superseded
Headers show
Series
  • [v7,01/42] target/arm: Add isar tests for mte
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Commit Message

Richard Henderson June 3, 2020, 1:13 a.m.
D1.10 specifies that exception handlers begin with tag checks overridden.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

---
v2: Only set if MTE feature present.
---
 target/arm/helper.c | 3 +++
 1 file changed, 3 insertions(+)

-- 
2.25.1

Patch

diff --git a/target/arm/helper.c b/target/arm/helper.c
index 3adafc07f0..50717afa4a 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -9702,6 +9702,9 @@  static void arm_cpu_do_interrupt_aarch64(CPUState *cs)
             break;
         }
     }
+    if (cpu_isar_feature(aa64_mte, cpu)) {
+        new_mode |= PSTATE_TCO;
+    }
 
     pstate_write(env, PSTATE_DAIF | new_mode);
     env->aarch64 = 1;