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[174.21.143.238]) by smtp.gmail.com with ESMTPSA id 3sm290067pfe.85.2020.06.02.18.14.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Jun 2020 18:14:10 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v7 40/42] target/arm: Cache the Tagged bit for a page in MemTxAttrs Date: Tue, 2 Jun 2020 18:13:15 -0700 Message-Id: <20200603011317.473934-41-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200603011317.473934-1-richard.henderson@linaro.org> References: <20200603011317.473934-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::644; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x644.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, steplong@quicinc.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This "bit" is a particular value of the page's MemAttr. Signed-off-by: Richard Henderson --- v6: Test HCR_EL2.{DC,DCT}; test Stage2 attributes. --- target/arm/helper.c | 43 +++++++++++++++++++++++++++++++++++-------- 1 file changed, 35 insertions(+), 8 deletions(-) -- 2.25.1 diff --git a/target/arm/helper.c b/target/arm/helper.c index 50717afa4a..74925010ea 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -10875,6 +10875,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, uint64_t descaddrmask; bool aarch64 = arm_el_is_aa64(env, el); bool guarded = false; + uint8_t memattr; /* TODO: This code does not support shareability levels. */ if (aarch64) { @@ -11099,17 +11100,32 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, txattrs->target_tlb_bit0 = true; } - if (cacheattrs != NULL) { + if (mmu_idx == ARMMMUIdx_Stage2) { + memattr = convert_stage2_attrs(env, extract32(attrs, 0, 4)); + } else { + /* Index into MAIR registers for cache attributes */ + uint64_t mair = env->cp15.mair_el[el]; + memattr = extract64(mair, extract32(attrs, 0, 3) * 8, 8); + } + + /* When MTE is enabled, remember Tagged Memory in IOTLB. */ + if (aarch64 && cpu_isar_feature(aa64_mte, cpu)) { if (mmu_idx == ARMMMUIdx_Stage2) { - cacheattrs->attrs = convert_stage2_attrs(env, - extract32(attrs, 0, 4)); + /* + * Require Normal, I+O Shareable, WB, NT, RA, WA (0xff). + * If not, squash stage1 tagged normal setting. + */ + if (memattr != 0xff) { + txattrs->target_tlb_bit1 = false; + } } else { - /* Index into MAIR registers for cache attributes */ - uint8_t attrindx = extract32(attrs, 0, 3); - uint64_t mair = env->cp15.mair_el[regime_el(env, mmu_idx)]; - assert(attrindx <= 7); - cacheattrs->attrs = extract64(mair, attrindx * 8, 8); + /* Tagged Normal Memory (0xf0). */ + txattrs->target_tlb_bit1 = (memattr == 0xf0); } + } + + if (cacheattrs != NULL) { + cacheattrs->attrs = memattr; cacheattrs->shareability = extract32(attrs, 6, 2); } @@ -12065,6 +12081,17 @@ bool get_phys_addr(CPUARMState *env, target_ulong address, *phys_ptr = address; *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; *page_size = TARGET_PAGE_SIZE; + + /* Stage1 translations are Tagged or Untagged based on HCR_DCT. */ + if (cpu_isar_feature(aa64_mte, env_archcpu(env)) + && (mmu_idx == ARMMMUIdx_Stage1_E0 || + mmu_idx == ARMMMUIdx_Stage1_E1 || + mmu_idx == ARMMMUIdx_Stage1_E1_PAN)) { + uint64_t hcr = arm_hcr_el2_eff(env); + if ((hcr & (HCR_DC | HCR_DCT)) == (HCR_DC | HCR_DCT)) { + attrs->target_tlb_bit1 = true; + } + } return 0; }