From patchwork Fri Jun 26 03:31:40 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 191802 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp116859ilg; Thu, 25 Jun 2020 21:01:47 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzQbeX0VzAlccVONalD3XSe4evZltmYu5jbZLlpQn58iPpRi2QwLk7TlCnI2nCIK2XuPpfk X-Received: by 2002:a25:cf0d:: with SMTP id f13mr1900797ybg.108.1593144107039; Thu, 25 Jun 2020 21:01:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1593144107; cv=none; d=google.com; s=arc-20160816; b=vAMKrgmHHeFljhAqsxlEUb/xb+6M7APNLZ0YCd64sDt/TFBLYaa7v8bWDEWsKjXevT ppexHcE1NVz8Vok1liMdRUcq4zFf/1vuDAPZuzf9A/bF6JKgANMJQICd6Ac1bw8uWGEl sMbyPuZlETMSLNDpmYEeLiK6GKg2kr+JJyPBPXyAPRLUK1Y3N+bTPbam2Mwfkt1VpAxq MI4rDE8IAN9aby/u48vapa4rh9sjhLSnfALcMMGzXl45w0+kQANmmxfxorRAA4ssxA1A tlildUx5B/Keb3jvnhWbXljh1iZdbqsB9L0H8j9vyWLmptRlA6LVIV4RtoiNRK3WzKuS WYAQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=japKMCqtTJyDaS3XobN6C3/Z94MHElZymKmMsjyLpI4=; b=wUr+Ak/DnK8/XQor9VwbYfBfTx31OVMuN5+f5j7tpJy/QVatnw+0n6Lr4BjCeG01vL wEWWv5zV8elACpxGdOweGCJ//Ulu+8+Wv/SDNpLqa5MktXykw6cUk5b4/F0oqc7qab7o CpZKfkE7PZWQClqTDSfSR7GB7JQ511V9f6uTmqD+AvNpxLZu2I1DW/NsLY3dGOpRLva7 MnJNhI+ElV2/3EiNjCasNLS28eclB2Cam6sleWnIubmKAxsRtDZhHJ7Mzo6giBaC/Jwa PDkoBPM94jw903Du+GnfaXU27JfACRMuLnfhrC6BKM8RhRYOUm1naP9xMY7vgbgwiufb +dNA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="P51XTj/S"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id m9si4476047ybo.98.2020.06.25.21.01.46 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 25 Jun 2020 21:01:47 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="P51XTj/S"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:57658 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jofYg-0005wa-Hm for patch@linaro.org; Fri, 26 Jun 2020 00:01:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:42970) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jof6c-0001Pp-3v for qemu-devel@nongnu.org; Thu, 25 Jun 2020 23:32:46 -0400 Received: from mail-pl1-x644.google.com ([2607:f8b0:4864:20::644]:38829) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jof6a-00027w-Fg for qemu-devel@nongnu.org; Thu, 25 Jun 2020 23:32:45 -0400 Received: by mail-pl1-x644.google.com with SMTP id d10so3756828pls.5 for ; Thu, 25 Jun 2020 20:32:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=japKMCqtTJyDaS3XobN6C3/Z94MHElZymKmMsjyLpI4=; b=P51XTj/SdzBcw3mubVvk8ocGw8WrWb9T4Inr/K0w31Ee8sfg3XL6P9okc0GeYVxi92 vSbw3QqvD51wl/nPx451MOHdgmj3hNJRGwQb6QB9oUGla9gw2prT12cNgpMnHhorpyH7 IPnR7hECYnuJutxFDTPlf9APqVY9gMhXQgSbWl+i9SANVsAyg+ig1fn66k5gYIz0tBsh 1+PWMHSMRSVbXyYU972+IpbiWe92eUMUcWTX9UqWlFvS9Vc9E+8L9mSkC/3wfPSdLIUV MSSQWqIYt3vRgHdiLlr9vLk1Eupvy2R38UCVIBAOhIpHOmMCvD3bCKDQlYLLEx2cbngi WZGA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=japKMCqtTJyDaS3XobN6C3/Z94MHElZymKmMsjyLpI4=; b=AEVbBFBu1hRRT4t4wMz+vnXV6IYj+qUO+uN0nXlHrv6lu/4gnCkd1u5fS42jsqMRNe zNUi9b9JTkCNkguTSC9zaelj/MnapNvq15lycx34zbE18eHPgx58HvbHYO7gEv1fRcnD zXJDLvtYVq6TAZWne8k/oq+IzRZEAOXkascX37cuMkLye2iXzmmEVZCI/z61tteWVSp/ /ko5OuTndj+sjSbkb1gcm5z2tacttKvFkOWxg9KTBUpPkD9ke/sAKHllyCPBfzHMwAqm BPDbrcEPStj+u4EMfU13sSpF1AQ/32X/qZYOiqPfERNHmyrquicVjMFDlXplfAmLiRIm ID1A== X-Gm-Message-State: AOAM5330owkvXR0DEEoJ3Uu32bwtRs2cZGxYscD2dijsFg2XaBJT12na LrWKhxDg68TuEsTnDU3XDGaxxPANXlc= X-Received: by 2002:a17:902:a504:: with SMTP id s4mr833003plq.337.1593142362784; Thu, 25 Jun 2020 20:32:42 -0700 (PDT) Received: from localhost.localdomain (174-21-143-238.tukw.qwest.net. [174.21.143.238]) by smtp.gmail.com with ESMTPSA id y27sm1605256pgc.56.2020.06.25.20.32.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Jun 2020 20:32:42 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v9 42/46] target/arm: Cache the Tagged bit for a page in MemTxAttrs Date: Thu, 25 Jun 2020 20:31:40 -0700 Message-Id: <20200626033144.790098-43-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200626033144.790098-1-richard.henderson@linaro.org> References: <20200626033144.790098-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::644; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x644.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, david.spickett@linaro.org, steplong@quicinc.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This "bit" is a particular value of the page's MemAttr. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v6: Test HCR_EL2.{DC,DCT}; test Stage2 attributes. v8: Fill in cacheattrs for S1 disabled; retain tagging when combining attributes; set mte_tagging in arm_cpu_tlb_fill. --- target/arm/helper.c | 48 ++++++++++++++++++++++++++++++++++++++--- target/arm/tlb_helper.c | 5 +++++ 2 files changed, 50 insertions(+), 3 deletions(-) -- 2.25.1 diff --git a/target/arm/helper.c b/target/arm/helper.c index 2072db2f92..dc9c29f998 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11834,9 +11834,19 @@ static uint8_t combine_cacheattr_nibble(uint8_t s1, uint8_t s2) */ static ARMCacheAttrs combine_cacheattrs(ARMCacheAttrs s1, ARMCacheAttrs s2) { - uint8_t s1lo = extract32(s1.attrs, 0, 4), s2lo = extract32(s2.attrs, 0, 4); - uint8_t s1hi = extract32(s1.attrs, 4, 4), s2hi = extract32(s2.attrs, 4, 4); + uint8_t s1lo, s2lo, s1hi, s2hi; ARMCacheAttrs ret; + bool tagged = false; + + if (s1.attrs == 0xf0) { + tagged = true; + s1.attrs = 0xff; + } + + s1lo = extract32(s1.attrs, 0, 4); + s2lo = extract32(s2.attrs, 0, 4); + s1hi = extract32(s1.attrs, 4, 4); + s2hi = extract32(s2.attrs, 4, 4); /* Combine shareability attributes (table D4-43) */ if (s1.shareability == 2 || s2.shareability == 2) { @@ -11884,6 +11894,11 @@ static ARMCacheAttrs combine_cacheattrs(ARMCacheAttrs s1, ARMCacheAttrs s2) } } + /* TODO: CombineS1S2Desc does not consider transient, only WB, RWA. */ + if (tagged && ret.attrs == 0xff) { + ret.attrs = 0xf0; + } + return ret; } @@ -11963,8 +11978,11 @@ bool get_phys_addr(CPUARMState *env, target_ulong address, * Normal Non-Shareable, * Inner Write-Back Read-Allocate Write-Allocate, * Outer Write-Back Read-Allocate Write-Allocate. + * Do not overwrite Tagged within attrs. */ - cacheattrs->attrs = 0xff; + if (cacheattrs->attrs != 0xf0) { + cacheattrs->attrs = 0xff; + } cacheattrs->shareability = 0; } *cacheattrs = combine_cacheattrs(*cacheattrs, cacheattrs2); @@ -12029,6 +12047,9 @@ bool get_phys_addr(CPUARMState *env, target_ulong address, /* Definitely a real MMU, not an MPU */ if (regime_translation_disabled(env, mmu_idx)) { + uint64_t hcr; + uint8_t memattr; + /* * MMU disabled. S1 addresses within aa64 translation regimes are * still checked for bounds -- see AArch64.TranslateAddressS1Off. @@ -12066,6 +12087,27 @@ bool get_phys_addr(CPUARMState *env, target_ulong address, *phys_ptr = address; *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; *page_size = TARGET_PAGE_SIZE; + + /* Fill in cacheattr a-la AArch64.TranslateAddressS1Off. */ + hcr = arm_hcr_el2_eff(env); + cacheattrs->shareability = 0; + if (hcr & HCR_DC) { + if (hcr & HCR_DCT) { + memattr = 0xf0; /* Tagged, Normal, WB, RWA */ + } else { + memattr = 0xff; /* Normal, WB, RWA */ + } + } else if (access_type == MMU_INST_FETCH) { + if (regime_sctlr(env, mmu_idx) & SCTLR_I) { + memattr = 0xee; /* Normal, WT, RA, NT */ + } else { + memattr = 0x44; /* Normal, NC, No */ + } + cacheattrs->shareability = 2; /* outer sharable */ + } else { + memattr = 0x00; /* Device, nGnRnE */ + } + cacheattrs->attrs = memattr; return 0; } diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c index 89d90465a3..b35dc8a011 100644 --- a/target/arm/tlb_helper.c +++ b/target/arm/tlb_helper.c @@ -188,6 +188,11 @@ bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size, phys_addr &= TARGET_PAGE_MASK; address &= TARGET_PAGE_MASK; } + /* Notice and record tagged memory. */ + if (cpu_isar_feature(aa64_mte, cpu) && cacheattrs.attrs == 0xf0) { + arm_tlb_mte_tagged(&attrs) = true; + } + tlb_set_page_with_attrs(cs, address, phys_addr, attrs, prot, mmu_idx, page_size); return true;