From patchwork Fri Jun 26 03:31:42 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 191803 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp117505ilg; Thu, 25 Jun 2020 21:02:38 -0700 (PDT) X-Google-Smtp-Source: ABdhPJycdhEIHoU9sp0wNpGZeNaPTbyMdjp06y8h1fFzOn80fiogMRU2C7LghJcsyz30ZYctKLn+ X-Received: by 2002:a25:8404:: with SMTP id u4mr1856046ybk.515.1593144158463; Thu, 25 Jun 2020 21:02:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1593144158; cv=none; d=google.com; s=arc-20160816; b=grXMNI5VdmxOXU2eS+HX/jHcbdZ6MVyRrxr16wHjz9i8Mk2liJbHmqqqjUQHIlO0wK g8FN2WCU6VlFC3V0yjxtSvj7onjyw2fIP6xb3B2WND4hBd+a713TCckfJWedMSbY0pyi X3Se+4NofZpnlVGdiul79fzGKmZotj/4pVOU35IUHU/WjW+3jS4oev3ud17Y1XvmqVyb AGQC7fgWmHChalSzlK12GlxZ/5tEZNmzWtdK5FE7dL3Oz8t4dM5RYu8NlLfU+jHdfc5O dLNCv/Z3h/MLuYlmRgdr0/ccJ+HYB+2q9FIeAd9KKD62E3Szv7j9vGVvnmPUCgm5UrQr e84g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=UjqghZMppldJJQFCz4puY4NIT8Id2WOfJG93PywKQl8=; b=Iw5N7yRaFZhwtl4EbHsyGei+Zs1ySquNbIgeWz2syC7Y8iRE/m8QmP2x1Y2SDyX253 S5CZ5NJYtEjp1jRUzhE5INbx3DTMX3K1ICvG5qQaS/Bc5wTsVVcrDVVGkOjfpYriD8Cj zvdZbMrkJ1Os2tt5Q0xPS/3vRSlmch8bnIk5lbgo1kYxS7kj9OXKQDHE7bgi2zZMKSPg KLIOidZ3/KGH6GeB3oQdsh9LqK7C0yDAoDhKRd/N5YAsQob+buUIRnnTE35n5tCiiTEN OSVxHBYydTZfPNMAztfncYOFp6orHcsEjlHhqrnZNVNSWSC54VA348fWRlOqYRkEOJlW DKGg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=oJQGPQmi; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id m21si25601602ybf.470.2020.06.25.21.02.38 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 25 Jun 2020 21:02:38 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=oJQGPQmi; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:60054 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jofZV-0006vf-Sb for patch@linaro.org; Fri, 26 Jun 2020 00:02:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43030) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jof6e-0001WQ-TR for qemu-devel@nongnu.org; Thu, 25 Jun 2020 23:32:48 -0400 Received: from mail-pf1-x442.google.com ([2607:f8b0:4864:20::442]:45238) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jof6d-00028s-3e for qemu-devel@nongnu.org; Thu, 25 Jun 2020 23:32:48 -0400 Received: by mail-pf1-x442.google.com with SMTP id a127so4037949pfa.12 for ; Thu, 25 Jun 2020 20:32:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=UjqghZMppldJJQFCz4puY4NIT8Id2WOfJG93PywKQl8=; b=oJQGPQmitKNtnEQOFZ7B040mdDpGJ4Li5laWEnkKtf4RvSCQFyKw0/0WtYXvQ+tEWj WL15tT6BTSX2t0WQrhuDua1AoJaFnP1G/EwcMaFeqZ0tOxjSsHjBMtvVoudjjhVBVzuE dJK8onjFX64H1rs9laiu29nKXDqi7eWGy10kQh0Hq6aly7cl6dkEChZjOe38xPST5v7f vx5A4xkrxN+6JPVGh2DAcBALWxV96xIpS7NaumWhe4HjaVoyPNRTRwdRLSxHU6mbgloK 0NZfMHGumE5oOKMUfGymHUoqr4VvK5jr7w0f1ny7bfE7tYis6I4XnJhq6oarJuFQm3t4 krSQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=UjqghZMppldJJQFCz4puY4NIT8Id2WOfJG93PywKQl8=; b=lX/P6FbY3c6pc2oUBIegkumKaY1XnKVKOGXrkricq2tuSOvgttiU4iyAO7cZrR+6x5 HTvD+WG1mbX/UOtv7gLeJuAbgM2klUVLgU9oTQokyiL7ZcoTPmy2Uomov5pkzajLVRNf 0bUcN7iy1BlSawCXAlymSZfJcMcJlzxBDZSdZ33PzXEawuMe0smMnmIFLiC9CONv1VPB 3OT1vLdik+yVyBzs56MBSW1Pwokw7qUwzj0rWh1hvyF1b7zldQjeb68kAzAVpUw8KqO+ QduBC4SrLPoG/D4Fw7Jrs1gh4af1XPIZRA7FIRadzD1obPaoxvMz7V98TAHJvX91FYL7 dC3w== X-Gm-Message-State: AOAM530hUmIR1GFCWGDTZ2uW2wp8YnaazVyeeGHW+/5IiU4Y7UdmDGo4 +ijwkeud2QUW1Or1YbTh83D30uOLZMM= X-Received: by 2002:a63:cf03:: with SMTP id j3mr947773pgg.24.1593142365268; Thu, 25 Jun 2020 20:32:45 -0700 (PDT) Received: from localhost.localdomain (174-21-143-238.tukw.qwest.net. [174.21.143.238]) by smtp.gmail.com with ESMTPSA id y27sm1605256pgc.56.2020.06.25.20.32.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Jun 2020 20:32:44 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v9 44/46] target/arm: Add allocation tag storage for system mode Date: Thu, 25 Jun 2020 20:31:42 -0700 Message-Id: <20200626033144.790098-45-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200626033144.790098-1-richard.henderson@linaro.org> References: <20200626033144.790098-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::442; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x442.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, david.spickett@linaro.org, steplong@quicinc.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Look up the physical address for the given virtual address, convert that to a tag physical address, and finally return the host address that backs it. Signed-off-by: Richard Henderson --- target/arm/mte_helper.c | 131 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 131 insertions(+) -- 2.25.1 Reviewed-by: Peter Maydell diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c index 4f9bd3add3..5ea57d487a 100644 --- a/target/arm/mte_helper.c +++ b/target/arm/mte_helper.c @@ -21,6 +21,7 @@ #include "cpu.h" #include "internals.h" #include "exec/exec-all.h" +#include "exec/ram_addr.h" #include "exec/cpu_ldst.h" #include "exec/helper-proto.h" @@ -74,8 +75,138 @@ static uint8_t *allocation_tag_mem(CPUARMState *env, int ptr_mmu_idx, int ptr_size, MMUAccessType tag_access, int tag_size, uintptr_t ra) { +#ifdef CONFIG_USER_ONLY /* Tag storage not implemented. */ return NULL; +#else + uintptr_t index; + CPUIOTLBEntry *iotlbentry; + int in_page, flags; + ram_addr_t ptr_ra; + hwaddr ptr_paddr, tag_paddr, xlat; + MemoryRegion *mr; + ARMASIdx tag_asi; + AddressSpace *tag_as; + void *host; + + /* + * Probe the first byte of the virtual address. This raises an + * exception for inaccessible pages, and resolves the virtual address + * into the softmmu tlb. + * + * When RA == 0, this is for mte_probe1. The page is expected to be + * valid. Indicate to probe_access_flags no-fault, then assert that + * we received a valid page. + */ + flags = probe_access_flags(env, ptr, ptr_access, ptr_mmu_idx, + ra == 0, &host, ra); + assert(!(flags & TLB_INVALID_MASK)); + + /* + * Find the iotlbentry for ptr. This *must* be present in the TLB + * because we just found the mapping. + * TODO: Perhaps there should be a cputlb helper that returns a + * matching tlb entry + iotlb entry. + */ + index = tlb_index(env, ptr_mmu_idx, ptr); +# ifdef CONFIG_DEBUG_TCG + { + CPUTLBEntry *entry = tlb_entry(env, ptr_mmu_idx, ptr); + target_ulong comparator = (ptr_access == MMU_DATA_LOAD + ? entry->addr_read + : tlb_addr_write(entry)); + g_assert(tlb_hit(comparator, ptr)); + } +# endif + iotlbentry = &env_tlb(env)->d[ptr_mmu_idx].iotlb[index]; + + /* If the virtual page MemAttr != Tagged, access unchecked. */ + if (!arm_tlb_mte_tagged(&iotlbentry->attrs)) { + return NULL; + } + + /* + * If not backed by host ram, there is no tag storage: access unchecked. + * This is probably a guest os bug though, so log it. + */ + if (unlikely(flags & TLB_MMIO)) { + qemu_log_mask(LOG_GUEST_ERROR, + "Page @ 0x%" PRIx64 " indicates Tagged Normal memory " + "but is not backed by host ram\n", ptr); + return NULL; + } + + /* + * The Normal memory access can extend to the next page. E.g. a single + * 8-byte access to the last byte of a page will check only the last + * tag on the first page. + * Any page access exception has priority over tag check exception. + */ + in_page = -(ptr | TARGET_PAGE_MASK); + if (unlikely(ptr_size > in_page)) { + void *ignore; + flags |= probe_access_flags(env, ptr + in_page, ptr_access, + ptr_mmu_idx, ra == 0, &ignore, ra); + assert(!(flags & TLB_INVALID_MASK)); + } + + /* Any debug exception has priority over a tag check exception. */ + if (unlikely(flags & TLB_WATCHPOINT)) { + int wp = ptr_access == MMU_DATA_LOAD ? BP_MEM_READ : BP_MEM_WRITE; + assert(ra != 0); + cpu_check_watchpoint(env_cpu(env), ptr, ptr_size, + iotlbentry->attrs, wp, ra); + } + + /* + * Find the physical address within the normal mem space. + * The memory region lookup must succeed because TLB_MMIO was + * not set in the cputlb lookup above. + */ + mr = memory_region_from_host(host, &ptr_ra); + tcg_debug_assert(mr != NULL); + tcg_debug_assert(memory_region_is_ram(mr)); + ptr_paddr = ptr_ra; + do { + ptr_paddr += mr->addr; + mr = mr->container; + } while (mr); + + /* Convert to the physical address in tag space. */ + tag_paddr = ptr_paddr >> (LOG2_TAG_GRANULE + 1); + + /* Look up the address in tag space. */ + tag_asi = iotlbentry->attrs.secure ? ARMASIdx_TagS : ARMASIdx_TagNS; + tag_as = cpu_get_address_space(env_cpu(env), tag_asi); + mr = address_space_translate(tag_as, tag_paddr, &xlat, NULL, + tag_access == MMU_DATA_STORE, + iotlbentry->attrs); + + /* + * Note that @mr will never be NULL. If there is nothing in the address + * space at @tag_paddr, the translation will return the unallocated memory + * region. For our purposes, the result must be ram. + */ + if (unlikely(!memory_region_is_ram(mr))) { + /* ??? Failure is a board configuration error. */ + qemu_log_mask(LOG_UNIMP, + "Tag Memory @ 0x%" HWADDR_PRIx " not found for " + "Normal Memory @ 0x%" HWADDR_PRIx "\n", + tag_paddr, ptr_paddr); + return NULL; + } + + /* + * Ensure the tag memory is dirty on write, for migration. + * Tag memory can never contain code or display memory (vga). + */ + if (tag_access == MMU_DATA_STORE) { + ram_addr_t tag_ra = memory_region_get_ram_addr(mr) + xlat; + cpu_physical_memory_set_dirty_flag(tag_ra, DIRTY_MEMORY_MIGRATION); + } + + return memory_region_get_ram_ptr(mr) + xlat; +#endif } uint64_t HELPER(irg)(CPUARMState *env, uint64_t rn, uint64_t rm)