[2/3] bindings: sound: Add documentation for TI j721e EVM (CPB and IVI)

diff --git a/Documentation/devicetree/bindings/sound/ti,j721e-cpb-audio.yaml b/Documentation/devicetree/bindings/sound/ti,j721e-cpb-audio.yaml
new file mode 100644
index 000000000000..0355ffc2b01b
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/ti,j721e-cpb-audio.yaml
@@ -0,0 +1,93 @@ 
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/ti,j721e-cpb-audio.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Texas Instruments J721e Common Processor Board Audio Support
+
+maintainers:
+  - Peter Ujfalusi <peter.ujfalusi@ti.com>
+
+description: |
+  The audio support on the board is using pcm3168a codec connected to McASP10
+  serializers in parallel setup.
+  The pcm3168a SCKI clock is sourced from j721e AUDIO_REFCLK2 pin.
+  In order to support 48KHz and 44.1KHz family of sampling rates the parent
+  clock for AUDIO_REFCLK2 needs to be changed between PLL4 (for 48KHz) and
+  PLL15 (for 44.1KHz). The same PLLs are used for McASP10's AUXCLK clock via
+  different HSDIVIDER.
+
+properties:
+  compatible:
+    items:
+      - const: ti,j721e-cpb-audio
+
+  model:
+    $ref: /schemas/types.yaml#/definitions/string
+    description: User specified audio sound card name
+
+  ti,cpb-mcasp:
+    description: phandle to McASP10
+    allOf:
+      - $ref: /schemas/types.yaml#/definitions/phandle
+
+  ti,cpb-codec:
+    description: phandle to the pcm3168a codec used on the CPB
+    allOf:
+      - $ref: /schemas/types.yaml#/definitions/phandle
+
+  clocks:
+    items:
+      - description: PLL4 clock
+      - description: PLL15 clock
+      - description: McASP10 auxclk clock
+      - description: PLL4_HSDIV0 parent for McASP10 auxclk (for 48KHz)
+      - description: PLL15_HSDIV0 parent for McASP10 auxclk (for 44.1KHz)
+      - description: AUDIO_REFCLK2 clock
+      - description: PLL4_HSDIV2 parent for AUDIO_REFCLK2 clock (for 48KHz)
+      - description: PLL15_HSDIV2 parent for AUDIO_REFCLK2 clock (for 44.1KHz)
+
+  clock-names:
+    items:
+      - const: pll4
+      - const: pll15
+      - const: cpb-mcasp
+      - const: cpb-mcasp-48000
+      - const: cpb-mcasp-44100
+      - const: audio-refclk2
+      - const: audio-refclk2-48000
+      - const: audio-refclk2-44100
+
+required:
+  - compatible
+  - model
+  - ti,cpb-mcasp
+  - ti,cpb-codec
+  - clocks
+  - clock-names
+
+additionalProperties: false
+
+examples:
+  - |+
+    sound {
+        compatible = "ti,j721e-cpb-audio";
+        model = "j721e-cpb";
+
+        status = "okay";
+
+        ti,cpb-mcasp = <&mcasp10>;
+        ti,cpb-codec = <&pcm3168a_1>;
+
+        clocks = <&pll4>, <&pll15>,
+                 <&k3_clks 184 1>,
+                 <&k3_clks 184 2>, <&k3_clks 184 4>,
+                 <&k3_clks 157 371>,
+                 <&k3_clks 157 400>, <&k3_clks 157 401>;
+        clock-names = "pll4", "pll15",
+                      "cpb-mcasp",
+                      "cpb-mcasp-48000", "cpb-mcasp-44100",
+                      "audio-refclk2",
+                      "audio-refclk2-48000", "audio-refclk2-44100";
+    };
diff --git a/Documentation/devicetree/bindings/sound/ti,j721e-cpb-ivi-audio.yaml b/Documentation/devicetree/bindings/sound/ti,j721e-cpb-ivi-audio.yaml
new file mode 100644
index 000000000000..d02c66926418
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/ti,j721e-cpb-ivi-audio.yaml
@@ -0,0 +1,145 @@ 
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/ti,j721e-cpb-audio.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Texas Instruments J721e Common Processor Board Audio Support
+
+maintainers:
+  - Peter Ujfalusi <peter.ujfalusi@ti.com>
+
+description: |
+  The Infotainment board plugs into the Common Processor Board, the support of the
+  extension board is extending the CPB audio support, decribed in:
+  sound/ti,j721e-cpb-audio.txt
+
+  The audio support on the Infotainment Expansion Board consists of McASP0
+  connected to two pcm3168a codecs with dedicated set of serializers to each.
+  The SCKI for pcm3168a is sourced from j721e AUDIO_REFCLK0 pin.
+
+  In order to support 48KHz and 44.1KHz family of sampling rates the parent clock
+  for AUDIO_REFCLK0 needs to be changed between PLL4 (for 48KHz) and PLL15 (for
+  44.1KHz). The same PLLs are used for McASP0's AUXCLK clock via different
+  HSDIVIDER.
+
+  Note: the same PLL4 and PLL15 is used by the audio support on the CPB!
+
+allOf:
+  - $ref: "ti,j721e-cpb-audio.yaml#"
+
+properties:
+  compatible:
+    items:
+      - const: ti,j721e-cpb-ivi-audio
+
+  model:
+    $ref: /schemas/types.yaml#/definitions/string
+    description: User specified audio sound card name
+
+  ti,cpb-mcasp:
+    description: phandle to McASP10
+    allOf:
+      - $ref: /schemas/types.yaml#/definitions/phandle
+
+  ti,cpb-codec:
+    description: phandle to the pcm3168a codec used on the CPB
+    allOf:
+      - $ref: /schemas/types.yaml#/definitions/phandle
+
+  ti,ivi-mcasp:
+    description: phandle to McASP9
+    allOf:
+      - $ref: /schemas/types.yaml#/definitions/phandle
+
+  ti,ivi-codec-a:
+    description: phandle to the pcm3168a-A codec on the expansion board
+    allOf:
+      - $ref: /schemas/types.yaml#/definitions/phandle
+
+  ti,ivi-codec-b:
+    description: phandle to the pcm3168a-B codec on the expansion board
+    allOf:
+      - $ref: /schemas/types.yaml#/definitions/phandle
+
+  clocks:
+    items:
+      - description: PLL4 clock
+      - description: PLL15 clock
+      - description: McASP10 auxclk clock
+      - description: PLL4_HSDIV0 parent for McASP10 auxclk (for 48KHz)
+      - description: PLL15_HSDIV0 parent for McASP10 auxclk (for 44.1KHz)
+      - description: AUDIO_REFCLK2 clock
+      - description: PLL4_HSDIV2 parent for AUDIO_REFCLK2 clock (for 48KHz)
+      - description: PLL15_HSDIV2 parent for AUDIO_REFCLK2 clock (for 44.1KHz)
+      - description: McASP0 auxclk clock
+      - description: PLL4_HSDIV0 parent for McASP0 auxclk (for 48KHz)
+      - description: PLL15_HSDIV0 parent for McASP0 auxclk (for 44.1KHz)
+      - description: AUDIO_REFCLK0 clock
+      - description: PLL4_HSDIV2 parent for AUDIO_REFCLK0 clock (for 48KHz)
+      - description: PLL15_HSDIV2 parent for AUDIO_REFCLK0 clock (for 44.1KHz)
+
+  clock-names:
+    items:
+      - const: pll4
+      - const: pll15
+      - const: cpb-mcasp
+      - const: cpb-mcasp-48000
+      - const: cpb-mcasp-44100
+      - const: audio-refclk2
+      - const: audio-refclk2-48000
+      - const: audio-refclk2-44100
+      - const: ivi-mcasp
+      - const: ivi-mcasp-48000
+      - const: ivi-mcasp-44100
+      - const: audio-refclk0
+      - const: audio-refclk0-48000
+      - const: audio-refclk0-44100
+
+required:
+  - compatible
+  - model
+  - ti,cpb-mcasp
+  - ti,cpb-codec
+  - ti,ivi-mcasp
+  - ti,ivi-codec-a
+  - ti,ivi-codec-b
+  - clocks
+  - clock-names
+
+additionalProperties: false
+
+examples:
+  - |+
+    sound0: sound@0 {
+        compatible = "ti,j721e-cpb-ivi-audio";
+        model = "j721e-cpb-ivi
+
+        status = "okay";
+
+        ti,cpb-mcasp = <&mcasp10>;
+        ti,cpb-codec = <&pcm3168a_1>;
+
+        ti,ivi-mcasp = <&mcasp0>;
+        ti,ivi-codec-a = <&pcm3168a_a>;
+        ti,ivi-codec-b = <&pcm3168a_b>;
+
+        clocks = <&pll4>, <&pll15>,
+                 <&k3_clks 184 1>,
+                 <&k3_clks 184 2>, <&k3_clks 184 4>,
+                 <&k3_clks 157 371>,
+                 <&k3_clks 157 400>, <&k3_clks 157 401>,
+                 <&k3_clks 174 1>,
+                 <&k3_clks 174 2>, <&k3_clks 174 4>,
+                 <&k3_clks 157 301>,
+                 <&k3_clks 157 330>, <&k3_clks 157 331>;
+        clock-names = "pll4", "pll15",
+                      "cpb-mcasp",
+                      "cpb-mcasp-48000", "cpb-mcasp-44100",
+                      "audio-refclk2",
+                      "audio-refclk2-48000", "audio-refclk2-44100",
+                      "ivi-mcasp",
+                      "ivi-mcasp-48000", "ivi-mcasp-44100",
+                      "audio-refclk0",
+                      "audio-refclk0-48000", "audio-refclk0-44100";
+    };