diff mbox series

[v3,10/17] PCI: Use correct delay in pci_bridge_wait_for_secondary_bus

Message ID 20200303132852.13184-11-stanspas@amazon.com
State New
Headers show
Series Improve PCI device post-reset readiness polling | expand

Commit Message

Stanislav Spassov March 3, 2020, 1:28 p.m. UTC 
From: Stanislav Spassov <stanspas@amazon.de>

PCI Express Base Specification r5.0 (May 22, 2019) details the rules
for device reset in Section 6.6.

For a Downstream Port that does not support Link speeds greater than
5.0 GT/s, the minimum waiting period before software is permitted to
send a Configuration Request after a Conventional Reset is 100ms
(PCI_RESET_DELAY).

For a Downstream Port that supports Link speeds greater than 5.0 GT/s
(such ports are required to be Data Link Layer Link Active Reporting
capable), the period is again 100ms but measured after the link has
become active (PCI_DL_UP_DELAY).

The delays for both cases above can be overridden independently, and
pci_bridge_wait_for_secondary_bus should use the appropriate one.

Signed-off-by: Stanislav Spassov <stanspas@amazon.de>
---
 drivers/pci/pci.c | 6 ++++++
 1 file changed, 6 insertions(+)
diff mbox series

Patch

diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index e4840dbf2d1c..7e08c5f38190 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -4736,6 +4736,12 @@  void pci_bridge_wait_for_secondary_bus(struct pci_dev *dev, bool sx_resume)
 	/* Take delay requirements into account */
 	if (sx_resume && dev->ignore_reset_delay_on_sx_resume)
 		delay = 0;
+	else if (pcie_downstream_port(dev) &&
+		 pcie_get_speed_cap(dev) > PCIE_SPEED_5_0GT &&
+		 dev->link_active_reporting)
+		delay = pci_bus_max_delay(dev->subordinate,
+					  PCI_INIT_EVENT_DL_UP,
+					  PCI_DL_UP_DELAY);
 	else
 		delay = pci_bus_max_delay(dev->subordinate,
 					  PCI_INIT_EVENT_RESET,