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[203.254.224.25]) by mx.google.com with ESMTP id cr3si10570374pbc.230.1969.12.31.16.00.00; Mon, 02 Sep 2013 05:13:40 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of rajeshwari.s@samsung.com designates 203.254.224.25 as permitted sender) client-ip=203.254.224.25; Received: from epcpsbgr1.samsung.com (u141.gpu120.samsung.co.kr [203.254.230.141]) by mailout2.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0MSH009MRZAR3VZ0@mailout2.samsung.com>; Mon, 02 Sep 2013 21:13:39 +0900 (KST) Received: from epcpsbgm2.samsung.com ( [172.20.52.123]) by epcpsbgr1.samsung.com (EPCPMTA) with SMTP id 16.1D.30629.2F084225; Mon, 02 Sep 2013 21:13:38 +0900 (KST) X-AuditID: cbfee68d-b7fe86d0000077a5-7f-522480f236e2 Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id C2.C6.05832.2F084225; Mon, 02 Sep 2013 21:13:38 +0900 (KST) Received: from localhost.localdomain.com ([107.108.73.95]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0MSH004D4ZABZW60@mmp2.samsung.com>; Mon, 02 Sep 2013 21:13:38 +0900 (KST) From: Rajeshwari S Shinde To: u-boot@lists.denx.de Cc: patches@linaro.org, sjg@chromium.org, mk7.kang@samsung.com, chander.kashyap@linaro.org, u-boot-review@google.com, Akshay Saraswat Subject: [PATCH 07/10] Exynos5420: Add support for 5420 in pinmux and gpio Date: Mon, 02 Sep 2013 17:45:08 +0530 Message-id: <1378124111-26145-8-git-send-email-rajeshwari.s@samsung.com> X-Mailer: git-send-email 1.7.11.7 In-reply-to: <1378124111-26145-1-git-send-email-rajeshwari.s@samsung.com> References: <1378124111-26145-1-git-send-email-rajeshwari.s@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrKLMWRmVeSWpSXmKPExsWyRsSkWvdTg0qQwanj1han/jxmtHi4/iaL RceRFkaLKYe/sFh827KN0WL5643sFm/3drI7sHvMbrjI4rFgU6nHnWt72DzO3tnB6NG3ZRVj AGsUl01Kak5mWWqRvl0CV8a5FQYFZ20rznb+ZmxgfGfYxcjJISFgInHk8St2CFtM4sK99Wxd jFwcQgJLGSUm7T3LCFO04NJedojEdEaJh98+MEE4XUwSU3Y+ZOli5OBgA6raeCIBpEFEQELi V/9VsGZmgQWMEhP6wTYIC3hJzL96DCzOIqAqcev4TVYQm1fAQ6Jt+hxmiGWKEjOWPAOr4RTw lPg+ZxuYLQRUs+boHkaQvRIC09kl5q1YzAYxSEDi2+RDYDdICMhKbDoANUdS4uCKGywTGIUX MDKsYhRNLUguKE5KLzLUK07MLS7NS9dLzs/dxAgM8tP/nvXuYLx9wPoQYzLQuInMUqLJ+cAo ySuJNzQ2M7IwNTE1NjK3NCNNWEmcV63FOlBIID2xJDU7NbUgtSi+qDQntfgQIxMHp1QDo+dM ZelVpaef/Tz+KZHrSSd/wdrle34ed2pak6vs4Po95+DstKk/PZNOcvc+rC4pyvb+qd6/Pt3L bb/eh3MLFp2dJ+zSLbjgeYa34qyvZm9c3vqvWNLivVLXx9TPbfPK85fd+WIcF55+N6/IeFf0 opKnJ/MCZbXTPrr8+F1QOKfmVCNX190J05VYijMSDbWYi4oTAWsi6KiIAgAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrEIsWRmVeSWpSXmKPExsVy+t9jQd1PDSpBBks/GFic+vOY0eLh+pss Fh1HWhgtphz+wmLxbcs2RovlrzeyW7zd28nuwO4xu+Eii8eCTaUed67tYfM4e2cHo0ffllWM AaxRDYw2GamJKalFCql5yfkpmXnptkrewfHO8aZmBoa6hpYW5koKeYm5qbZKLj4Bum6ZOUB3 KCmUJeaUAoUCEouLlfTtME0IDXHTtYBpjND1DQmC6zEyQAMJaxgzzq0wKDhrW3G28zdjA+M7 wy5GTg4JAROJBZf2skPYYhIX7q1n62Lk4hASmM4o8fDbByYIp4tJYsrOhyxdjBwcbEAdG08k gDSICEhI/Oq/yghiMwssYJSY0A82SFjAS2L+1WNgcRYBVYlbx2+ygti8Ah4SbdPnMEMsU5SY seQZWA2ngKfE9znbwGwhoJo1R/cwTmDkXcDIsIpRNLUguaA4KT3XSK84Mbe4NC9dLzk/dxMj OIaeSe9gXNVgcYhRgINRiYdXYZlykBBrYllxZe4hRgkOZiUR3oZqlSAh3pTEyqrUovz4otKc 1OJDjMlAV01klhJNzgfGd15JvKGxibmpsamliYWJmSVpwkrivAdbrQOFBNITS1KzU1MLUotg tjBxcEo1MLqULPPe8/uEcHt8cP6mc2F1dbK7LKYdyH9msvMFR/Fdo427jsYf6JOf184a4arJ HVGeVnPFnXMBX+/B9SkPv9f5SqhlBFicaajvvyc39+ch32qdC/Wvm4vWvbDh9DpVn/L/u+AU s5Otfes+6Cmfv3timtWirJDIX44LNMLPfp0c8j6yWPXNTyWW4oxEQy3mouJEAHxidy3lAgAA DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: rajeshwari.s@samsung.com X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.128.172 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , From: Akshay Saraswat Adds code in pinmux and gpio framework to support Exynos5420. Signed-off-by: Rajeshwari S Shinde Signed-off-by: Akshay Saraswat --- arch/arm/cpu/armv7/exynos/pinmux.c | 171 +++++++++++++++++++++++++++++++- arch/arm/include/asm/arch-exynos/gpio.h | 52 ++++++++++ 2 files changed, 220 insertions(+), 3 deletions(-) diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c b/arch/arm/cpu/armv7/exynos/pinmux.c index 1b05ebf..0382176 100644 --- a/arch/arm/cpu/armv7/exynos/pinmux.c +++ b/arch/arm/cpu/armv7/exynos/pinmux.c @@ -46,6 +46,41 @@ static void exynos5_uart_config(int peripheral) } } +static void exynos5420_uart_config(int peripheral) +{ + struct exynos5420_gpio_part1 *gpio1 = + (struct exynos5420_gpio_part1 *)samsung_get_base_gpio_part1(); + struct s5p_gpio_bank *bank; + int i, start, count; + + switch (peripheral) { + case PERIPH_ID_UART0: + bank = &gpio1->a0; + start = 0; + count = 4; + break; + case PERIPH_ID_UART1: + bank = &gpio1->a0; + start = 4; + count = 4; + break; + case PERIPH_ID_UART2: + bank = &gpio1->a1; + start = 0; + count = 4; + break; + case PERIPH_ID_UART3: + bank = &gpio1->a1; + start = 4; + count = 2; + break; + } + for (i = start; i < start + count; i++) { + s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE); + s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2)); + } +} + static int exynos5_mmc_config(int peripheral, int flags) { struct exynos5_gpio_part1 *gpio1 = @@ -101,6 +136,62 @@ static int exynos5_mmc_config(int peripheral, int flags) return 0; } +static int exynos5420_mmc_config(int peripheral, int flags) +{ + struct exynos5420_gpio_part3 *gpio3 = + (struct exynos5420_gpio_part3 *)samsung_get_base_gpio_part3(); + struct s5p_gpio_bank *bank = NULL, *bank_ext = NULL; + int i, start = 0, gpio_func = 0; + + switch (peripheral) { + case PERIPH_ID_SDMMC0: + bank = &gpio3->c0; + bank_ext = &gpio3->c3; + start = 0; + gpio_func = GPIO_FUNC(0x2); + break; + case PERIPH_ID_SDMMC1: + bank = &gpio3->c1; + bank_ext = &gpio3->d1; + start = 4; + gpio_func = GPIO_FUNC(0x2); + break; + case PERIPH_ID_SDMMC2: + bank = &gpio3->c2; + bank_ext = NULL; + gpio_func = GPIO_FUNC(0x2); + break; + } + if ((flags & PINMUX_FLAG_8BIT_MODE) && !bank_ext) { + debug("SDMMC device %d does not support 8bit mode", + peripheral); + return -1; + } + if (flags & PINMUX_FLAG_8BIT_MODE) { + for (i = start; i <= (start + 3); i++) { + s5p_gpio_cfg_pin(bank_ext, i, gpio_func); + s5p_gpio_set_pull(bank_ext, i, GPIO_PULL_UP); + s5p_gpio_set_drv(bank_ext, i, GPIO_DRV_4X); + } + } + for (i = 0; i < 3; i++) { + s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2)); + s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE); + s5p_gpio_set_drv(bank, i, GPIO_DRV_4X); + } + + if (peripheral == PERIPH_ID_SDMMC0) + s5p_gpio_set_pull(bank, 2, GPIO_PULL_UP); + + for (i = 3; i <= 6; i++) { + s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2)); + s5p_gpio_set_pull(bank, i, GPIO_PULL_UP); + s5p_gpio_set_drv(bank, i, GPIO_DRV_4X); + } + + return 0; +} + static void exynos5_sromc_config(int flags) { struct exynos5_gpio_part1 *gpio1 = @@ -269,6 +360,49 @@ void exynos5_spi_config(int peripheral) } } +void exynos5420_spi_config(int peripheral) +{ + int cfg = 0, pin = 0, i; + struct s5p_gpio_bank *bank = NULL; + struct exynos5420_gpio_part1 *gpio1 = + (struct exynos5420_gpio_part1 *)samsung_get_base_gpio_part1(); + struct exynos5420_gpio_part4 *gpio4 = + (struct exynos5420_gpio_part4 *)samsung_get_base_gpio_part4(); + + switch (peripheral) { + case PERIPH_ID_SPI0: + bank = &gpio1->a2; + cfg = GPIO_FUNC(0x2); + pin = 0; + break; + case PERIPH_ID_SPI1: + bank = &gpio1->a2; + cfg = GPIO_FUNC(0x2); + pin = 4; + break; + case PERIPH_ID_SPI2: + bank = &gpio1->b1; + cfg = GPIO_FUNC(0x5); + pin = 1; + break; + case PERIPH_ID_SPI3: + bank = &gpio4->f1; + cfg = GPIO_FUNC(0x2); + pin = 0; + break; + case PERIPH_ID_SPI4: + for (i = 0; i < 2; i++) { + s5p_gpio_cfg_pin(&gpio4->f0, i + 2, GPIO_FUNC(0x4)); + s5p_gpio_cfg_pin(&gpio4->e0, i + 4, GPIO_FUNC(0x4)); + } + break; + } + if (peripheral != PERIPH_ID_SPI4) { + for (i = pin; i < pin + 4; i++) + s5p_gpio_cfg_pin(bank, i, cfg); + } +} + static int exynos5_pinmux_config(int peripheral, int flags) { switch (peripheral) { @@ -314,6 +448,35 @@ static int exynos5_pinmux_config(int peripheral, int flags) return 0; } +static int exynos5420_pinmux_config(int peripheral, int flags) +{ + switch (peripheral) { + case PERIPH_ID_UART0: + case PERIPH_ID_UART1: + case PERIPH_ID_UART2: + case PERIPH_ID_UART3: + exynos5420_uart_config(peripheral); + break; + case PERIPH_ID_SDMMC0: + case PERIPH_ID_SDMMC1: + case PERIPH_ID_SDMMC2: + case PERIPH_ID_SDMMC3: + return exynos5420_mmc_config(peripheral, flags); + case PERIPH_ID_SPI0: + case PERIPH_ID_SPI1: + case PERIPH_ID_SPI2: + case PERIPH_ID_SPI3: + case PERIPH_ID_SPI4: + exynos5420_spi_config(peripheral); + break; + default: + debug("%s: invalid peripheral %d", __func__, peripheral); + return -1; + } + + return 0; +} + static void exynos4_i2c_config(int peripheral, int flags) { struct exynos4_gpio_part1 *gpio1 = @@ -463,11 +626,13 @@ static int exynos4_pinmux_config(int peripheral, int flags) int exynos_pinmux_config(int peripheral, int flags) { - if (cpu_is_exynos5()) + if (cpu_is_exynos5()) { + if (proid_is_exynos5420()) + return exynos5420_pinmux_config(peripheral, flags); return exynos5_pinmux_config(peripheral, flags); - else if (cpu_is_exynos4()) + } else if (cpu_is_exynos4()) { return exynos4_pinmux_config(peripheral, flags); - else { + } else { debug("pinmux functionality not supported\n"); return -1; } diff --git a/arch/arm/include/asm/arch-exynos/gpio.h b/arch/arm/include/asm/arch-exynos/gpio.h index a1a7439..f892933 100644 --- a/arch/arm/include/asm/arch-exynos/gpio.h +++ b/arch/arm/include/asm/arch-exynos/gpio.h @@ -127,6 +127,58 @@ struct exynos4x12_gpio_part4 { struct s5p_gpio_bank v4; }; +struct exynos5420_gpio_part1 { + struct s5p_gpio_bank a0; + struct s5p_gpio_bank a1; + struct s5p_gpio_bank a2; + struct s5p_gpio_bank b0; + struct s5p_gpio_bank b1; + struct s5p_gpio_bank b2; + struct s5p_gpio_bank b3; + struct s5p_gpio_bank b4; + struct s5p_gpio_bank h0; +}; + +struct exynos5420_gpio_part2 { + struct s5p_gpio_bank y7; /* 0x1340_0000 */ + struct s5p_gpio_bank res[0x5f]; /* */ + struct s5p_gpio_bank x0; /* 0x1340_0C00 */ + struct s5p_gpio_bank x1; /* 0x1340_0C20 */ + struct s5p_gpio_bank x2; /* 0x1340_0C40 */ + struct s5p_gpio_bank x3; /* 0x1340_0C60 */ +}; + +struct exynos5420_gpio_part3 { + struct s5p_gpio_bank c0; + struct s5p_gpio_bank c1; + struct s5p_gpio_bank c2; + struct s5p_gpio_bank c3; + struct s5p_gpio_bank c4; + struct s5p_gpio_bank d1; + struct s5p_gpio_bank y0; + struct s5p_gpio_bank y1; + struct s5p_gpio_bank y2; + struct s5p_gpio_bank y3; + struct s5p_gpio_bank y4; + struct s5p_gpio_bank y5; + struct s5p_gpio_bank y6; +}; + +struct exynos5420_gpio_part4 { + struct s5p_gpio_bank e0; /* 0x1400_0000 */ + struct s5p_gpio_bank e1; /* 0x1400_0020 */ + struct s5p_gpio_bank f0; /* 0x1400_0040 */ + struct s5p_gpio_bank f1; /* 0x1400_0060 */ + struct s5p_gpio_bank g0; /* 0x1400_0080 */ + struct s5p_gpio_bank g1; /* 0x1400_00A0 */ + struct s5p_gpio_bank g2; /* 0x1400_00C0 */ + struct s5p_gpio_bank j4; /* 0x1400_00E0 */ +}; + +struct exynos5420_gpio_part5 { + struct s5p_gpio_bank z0; /* 0x0386_0000 */ +}; + struct exynos5_gpio_part1 { struct s5p_gpio_bank a0; struct s5p_gpio_bank a1;