diff mbox series

[v3,1/3] v4l2-dv-timings: Add timings for 1920x1080P48 and 4KP48

Message ID 20200618053304.14551-2-vishal.sagar@xilinx.com
State New
Headers show
Series Add support for Xilinx UHD-SDI Receiver subsystem | expand

Commit Message

Vishal Sagar June 18, 2020, 5:33 a.m. UTC 
Add the timing entry for 1920x1080p48, 3840x2160p48 and 4096x2160p48
from CTA-861-G.
1920x1080p48 is VIC 111.
3840x2160P48 is VIC 114.
4096x2160P48 is VIC 115.

Signed-off-by: Vishal Sagar <vishal.sagar@xilinx.com>
---
v3
- Added for first time

 include/uapi/linux/v4l2-dv-timings.h | 31 +++++++++++++++++++++++++++-
 1 file changed, 30 insertions(+), 1 deletion(-)
diff mbox series

Patch

diff --git a/include/uapi/linux/v4l2-dv-timings.h b/include/uapi/linux/v4l2-dv-timings.h
index b52b67c62562..6ceaa7841923 100644
--- a/include/uapi/linux/v4l2-dv-timings.h
+++ b/include/uapi/linux/v4l2-dv-timings.h
@@ -167,6 +167,16 @@ 
 		V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 20) \
 }
 
+#define V4L2_DV_BT_CEA_1920X1080P48 { \
+	.type = V4L2_DV_BT_656_1120, \
+	V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \
+		V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
+		148500000, 638, 44, 148, 4, 5, 36, 0, 0, 0, \
+		V4L2_DV_BT_STD_CEA861, \
+		V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
+		V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 111) \
+}
+
 #define V4L2_DV_BT_CEA_1920X1080P50 { \
 	.type = V4L2_DV_BT_656_1120, \
 	V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \
@@ -229,6 +239,16 @@ 
 		{ 0, 0 }, 95, 1) \
 }
 
+#define V4L2_DV_BT_CEA_3840X2160P48 { \
+	.type = V4L2_DV_BT_656_1120, \
+	V4L2_INIT_BT_TIMINGS(3840, 2160, 0, \
+		V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
+		594000000, 1276, 88, 296, 8, 10, 72, 0, 0, 0, \
+		V4L2_DV_BT_STD_CEA861, \
+		V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
+		V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 114) \
+}
+
 #define V4L2_DV_BT_CEA_3840X2160P50 { \
 	.type = V4L2_DV_BT_656_1120, \
 	V4L2_INIT_BT_TIMINGS(3840, 2160, 0, \
@@ -278,6 +298,16 @@ 
 		V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 100) \
 }
 
+#define V4L2_DV_BT_CEA_4096X2160P48 { \
+	.type = V4L2_DV_BT_656_1120, \
+	V4L2_INIT_BT_TIMINGS(4096, 2160, 0, \
+		V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
+		594000000, 1020, 88, 296, 8, 10, 72, 0, 0, 0, \
+		V4L2_DV_BT_STD_CEA861, \
+		V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
+		V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 115) \
+}
+
 #define V4L2_DV_BT_CEA_4096X2160P50 { \
 	.type = V4L2_DV_BT_656_1120, \
 	V4L2_INIT_BT_TIMINGS(4096, 2160, 0, \
@@ -297,7 +327,6 @@ 
 		V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 102) \
 }
 
-
 /* VESA Discrete Monitor Timings as per version 1.0, revision 12 */
 
 #define V4L2_DV_BT_DMT_640X350P85 { \