From patchwork Fri Mar 13 11:41:09 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomi Valkeinen X-Patchwork-Id: 210638 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.9 required=3.0 tests=DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2684AC10DCE for ; Fri, 13 Mar 2020 11:41:50 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id F391920724 for ; Fri, 13 Mar 2020 11:41:49 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="Bp8J830a" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726546AbgCMLlt (ORCPT ); Fri, 13 Mar 2020 07:41:49 -0400 Received: from lelv0142.ext.ti.com ([198.47.23.249]:48702 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726393AbgCMLlt (ORCPT ); Fri, 13 Mar 2020 07:41:49 -0400 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 02DBfjeO123434; Fri, 13 Mar 2020 06:41:45 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1584099705; bh=yimsxmb11KsAN8TinOtJPb9i7ZSt2cVpWmOVh/qfbUg=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=Bp8J830aggWFtAL+BANv4Th04S1MCA1UEyKD4aVj804XWSTrTiwb2f0E8xcMwrlCy CIxHU4FXZiCFC5pXQYzHqDoaq5t6b3v1x/QkzXniU4ebG1rrrWPxVlmRHLlzojvPZz p+vRTpt5POtdUiSpZs0ZynZr+ZJpX02JJY9veq18= Received: from DLEE108.ent.ti.com (dlee108.ent.ti.com [157.170.170.38]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 02DBfj4h010626 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 13 Mar 2020 06:41:45 -0500 Received: from DLEE107.ent.ti.com (157.170.170.37) by DLEE108.ent.ti.com (157.170.170.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3; Fri, 13 Mar 2020 06:41:45 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE107.ent.ti.com (157.170.170.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3 via Frontend Transport; Fri, 13 Mar 2020 06:41:45 -0500 Received: from deskari.lan (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 02DBfcom044014; Fri, 13 Mar 2020 06:41:44 -0500 From: Tomi Valkeinen To: , Benoit Parrot CC: Mauro Carvalho Chehab , Laurent Pinchart , Tomi Valkeinen Subject: [PATCH 04/16] media: ti-vpe: cal: print errors on timeouts Date: Fri, 13 Mar 2020 13:41:09 +0200 Message-ID: <20200313114121.32182-4-tomi.valkeinen@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200313114121.32182-1-tomi.valkeinen@ti.com> References: <20200313114121.32182-1-tomi.valkeinen@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org The driver does not print any errors on ComplexIO reset timeout or when waiting for stop-state, making it difficult to debug and notice problems. Add error prints for these cases. Signed-off-by: Tomi Valkeinen --- drivers/media/platform/ti-vpe/cal.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/media/platform/ti-vpe/cal.c b/drivers/media/platform/ti-vpe/cal.c index f6ce0558752a..1499d443f414 100644 --- a/drivers/media/platform/ti-vpe/cal.c +++ b/drivers/media/platform/ti-vpe/cal.c @@ -842,6 +842,11 @@ static void csi2_wait_for_phy(struct cal_ctx *ctx) reg_read(ctx->dev, CAL_CSI2_COMPLEXIO_CFG(ctx->csi2_port)), i, (i >= 250) ? "(timeout)" : ""); + if (reg_read_field(ctx->dev, CAL_CSI2_COMPLEXIO_CFG(ctx->csi2_port), + CAL_CSI2_COMPLEXIO_CFG_RESET_DONE_MASK) != + CAL_CSI2_COMPLEXIO_CFG_RESET_DONE_RESETCOMPLETED) + ctx_err(ctx, "Timeout waiting for Complex IO reset done\n"); + /* 4. G. Wait for all enabled lane to reach stop state */ for (i = 0; i < 10; i++) { if (reg_read_field(ctx->dev, @@ -855,6 +860,9 @@ static void csi2_wait_for_phy(struct cal_ctx *ctx) ctx->csi2_port, reg_read(ctx->dev, CAL_CSI2_TIMING(ctx->csi2_port)), (i >= 10) ? "(timeout)" : ""); + if (reg_read_field(ctx->dev, CAL_CSI2_TIMING(ctx->csi2_port), + CAL_CSI2_TIMING_FORCE_RX_MODE_IO1_MASK) != 0) + ctx_err(ctx, "Timeout waiting for stop state\n"); ctx_dbg(1, ctx, "CSI2_%d_REG1 = 0x%08x (Bit(31,28) should be set!)\n", (ctx->csi2_port - 1), reg_read(ctx->cc, CAL_CSI2_PHY_REG1));