@@ -18,6 +18,7 @@
#define HISI_SFC_V3XX_VERSION (0x1f8)
#define HISI_SFC_V3XX_CMD_CFG (0x300)
+#define HISI_SFC_V3XX_CMD_CFG_LOCK BIT(20)
#define HISI_SFC_V3XX_CMD_CFG_DUAL_IN_DUAL_OUT (1 << 17)
#define HISI_SFC_V3XX_CMD_CFG_DUAL_IO (2 << 17)
#define HISI_SFC_V3XX_CMD_CFG_FULL_DIO (3 << 17)
@@ -41,6 +42,34 @@ struct hisi_sfc_v3xx_host {
int max_cmd_dword;
};
+int hisi_sfc_v3xx_op_prepare(struct spi_mem *mem)
+{
+ struct spi_device *spi = mem->spi;
+ struct hisi_sfc_v3xx_host *host;
+ u32 reg = HISI_SFC_V3XX_CMD_CFG_LOCK;
+
+ host = spi_controller_get_devdata(spi->master);
+
+ writel(reg, host->regbase + HISI_SFC_V3XX_CMD_CFG);
+
+ reg = readl(host->regbase + HISI_SFC_V3XX_CMD_CFG);
+ if (!(reg & HISI_SFC_V3XX_CMD_CFG_LOCK))
+ return -EIO;
+
+ return 0;
+}
+
+void hisi_sfc_v3xx_op_unprepare(struct spi_mem *mem)
+{
+ struct spi_device *spi = mem->spi;
+ struct hisi_sfc_v3xx_host *host;
+
+ host = spi_controller_get_devdata(spi->master);
+
+ /* Release the lock and clear the command register. */
+ writel(0, host->regbase + HISI_SFC_V3XX_CMD_CFG);
+}
+
#define HISI_SFC_V3XX_WAIT_TIMEOUT_US 1000000
#define HISI_SFC_V3XX_WAIT_POLL_INTERVAL_US 10
@@ -163,7 +192,15 @@ static int hisi_sfc_v3xx_generic_exec_op(struct hisi_sfc_v3xx_host *host,
u8 chip_select)
{
int ret, len = op->data.nbytes;
- u32 config = 0;
+ u32 config;
+
+ /*
+ * The lock bit is in the command register. Clear the command
+ * field with lock bit held if it has been set in
+ * .prepare().
+ */
+ config = readl(host->regbase + HISI_SFC_V3XX_CMD_CFG);
+ config &= HISI_SFC_V3XX_CMD_CFG_LOCK;
if (op->addr.nbytes)
config |= HISI_SFC_V3XX_CMD_CFG_ADDR_EN_MSK;
@@ -248,6 +285,8 @@ static int hisi_sfc_v3xx_exec_op(struct spi_mem *mem,
static const struct spi_controller_mem_ops hisi_sfc_v3xx_mem_ops = {
.adjust_op_size = hisi_sfc_v3xx_adjust_op_size,
+ .prepare = hisi_sfc_v3xx_op_prepare,
+ .unprepare = hisi_sfc_v3xx_op_unprepare,
.exec_op = hisi_sfc_v3xx_exec_op,
};
The controller can be shared with the firmware, which may cause race problems. As most read/write/erase/lock/unlock of spi-nor flash are composed of a set of operations, while the firmware may use the controller and start its own operation in the middle of the process started by the kernel driver, which may lead to the kernel driver's function broken. Bit[20] in HISI_SFC_V3XX_CMD_CFG register plays a role of a lock, to protect the controller from firmware access, which means the firmware cannot reach the controller if the driver set the bit. Add prepare/ unprepare methods for the controller, we'll hold the lock in prepare method and release it in unprepare method, which will solve the race issue. Signed-off-by: Yicong Yang <yangyicong@hisilicon.com> --- drivers/spi/spi-hisi-sfc-v3xx.c | 41 ++++++++++++++++++++++++++++++++++++++++- 1 file changed, 40 insertions(+), 1 deletion(-)