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[212.159.14.18]) by mx.google.com with ESMTP id pe6si11964480wjb.2.2013.11.12.08.57.26 for ; Tue, 12 Nov 2013 08:57:27 -0800 (PST) Received-SPF: neutral (google.com: 212.159.14.18 is neither permitted nor denied by best guess record for domain of ed@camswl.com) client-ip=212.159.14.18; Received: from [192.168.1.112] ([88.98.47.97]) by avasout06 with smtp id ogxR1m00925obN001gxSFR; Tue, 12 Nov 2013 16:57:26 +0000 X-CM-Score: 0.00 X-CNFS-Analysis: v=2.1 cv=T8a1EZ6Q c=1 sm=1 tr=0 a=9EVhjF2u/PaHqPV12Jx4dQ==:117 a=9EVhjF2u/PaHqPV12Jx4dQ==:17 a=0Bzu9jTXAAAA:8 a=qGToLarIwtsA:10 a=yHkIrnhuIFAA:10 a=yj2z6k84kjkA:10 a=IkcTkHD0fZMA:10 a=EO40a-L4AAAA:8 a=gxTaDxXrldwA:10 a=KKAkSRfTAAAA:8 a=Sdha1zBqd7PNrsv4uzIA:9 a=QEXdDO2ut3YA:10 a=WwgC8nHKvroA:10 X-AUTH: ednevill:2500 Message-ID: <1384275445.29988.5.camel@localhost.localdomain> Subject: Implement READ/WRITE memory barriers From: Edward Nevill Reply-To: ed@camswl.com To: "aarch64-port-dev@openjdk.java.net" Cc: patches@linaro.org Date: Tue, 12 Nov 2013 16:57:25 +0000 X-Mailer: Evolution 3.8.3 (3.8.3-2.fc19) Mime-Version: 1.0 X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: ed@camswl.com X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.128.178 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Hi folks, The following patch implements READ/WRITE memory barriers in orderAccess_linux_aarch64.inline.hpp. These were apparently unimplemented although FULL memory barrier was implemented. I had actually looked at this code before and tricked myself into believing it was correct, probably because of all the #ifdef ARM / #ifed PPC etc etc. I have deleted all the #ifdef nonsense, the file is called XXX_aarch64.inline.hpp, if you use it on any other arch that is your problem! The implementation now comes down to 3 lines. #define FULL_MEM_BARRIER __sync_synchronize() // dmb ish #define READ_MEM_BARRIER __asm __volatile ("dmb ishld":::"memory") #define WRITE_MEM_BARRIER __asm __volatile ("dmb ishst":::"memory") OK to push? Ed. --- CUT HERE --- # HG changeset patch # User Edward Nevill edward.nevill@linaro.org # Date 1384274980 0 # Tue Nov 12 16:49:40 2013 +0000 # Node ID 6f3af7dcec4978ed0ebc8c1ebcbce7300f5d69ed # Parent 19d511645e2ed8b664fca4cecabf6eb3c2b75fb5 Implement READ/WRITE mem barriers diff -r 19d511645e2e -r 6f3af7dcec49 src/os_cpu/linux_aarch64/vm/orderAccess_linux_aarch64.inline.hpp --- a/src/os_cpu/linux_aarch64/vm/orderAccess_linux_aarch64.inline.hpp Sat Nov 09 11:20:38 2013 +0000 +++ b/src/os_cpu/linux_aarch64/vm/orderAccess_linux_aarch64.inline.hpp Tue Nov 12 16:49:40 2013 +0000 @@ -31,42 +31,9 @@ #include "runtime/os.hpp" #include "vm_version_aarch64.hpp" -#ifdef ARM - -/* - * ARM Kernel helper for memory barrier. - * Using __asm __volatile ("":::"memory") does not work reliable on ARM - * and gcc __sync_synchronize(); implementation does not use the kernel - * helper for all gcc versions so it is unreliable to use as well. - */ -typedef void (__kernel_dmb_t) (void); -#define __kernel_dmb (*(__kernel_dmb_t *) 0xffff0fa0) - -#define FULL_MEM_BARRIER __kernel_dmb() -#define READ_MEM_BARRIER __kernel_dmb() -#define WRITE_MEM_BARRIER __kernel_dmb() - -#else // ARM - -#define FULL_MEM_BARRIER __sync_synchronize() - -#ifdef PPC - -#define READ_MEM_BARRIER __asm __volatile ("isync":::"memory") -#ifdef __NO_LWSYNC__ -#define WRITE_MEM_BARRIER __asm __volatile ("sync":::"memory") -#else -#define WRITE_MEM_BARRIER __asm __volatile ("lwsync":::"memory") -#endif - -#else // PPC - -#define READ_MEM_BARRIER __asm __volatile ("":::"memory") -#define WRITE_MEM_BARRIER __asm __volatile ("":::"memory") - -#endif // PPC - -#endif // ARM +#define FULL_MEM_BARRIER __sync_synchronize() // dmb ish +#define READ_MEM_BARRIER __asm __volatile ("dmb ishld":::"memory") +#define WRITE_MEM_BARRIER __asm __volatile ("dmb ishst":::"memory") // Implementation of class OrderAccess. --- CUT HERE ---