[v3,4/4] docs: watchdog: mlx-wdt: Add description of new watchdog type 3

Message ID 20200503053424.31943-5-michaelsh@mellanox.com
State New
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  • Untitled series #39683
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Commit Message

michaelsh@mellanox.com May 3, 2020, 5:34 a.m.
From: Michael Shych <michaelsh@mellanox.com>

Add documentation with details of new type of Mellanox watchdog driver.

Signed-off-by: Michael Shych <michaelsh@mellanox.com>
Reviewed-by: Vadim Pasternak <vadimp@mellanox.com>
Add explanation about device registers order
Remove note about cpu_to_le16 and vice versa conversion
 Documentation/watchdog/mlx-wdt.rst | 10 ++++++++++
 1 file changed, 10 insertions(+)


diff --git a/Documentation/watchdog/mlx-wdt.rst b/Documentation/watchdog/mlx-wdt.rst
index bf5bafac47f0..35e690dea9db 100644
--- a/Documentation/watchdog/mlx-wdt.rst
+++ b/Documentation/watchdog/mlx-wdt.rst
@@ -24,10 +24,19 @@  Type 2:
   Maximum timeout is 255 sec.
   Get time-left is supported.
+Type 3:
+  Same as Type 2 with extended maximum timeout period.
+  Maximum timeout is 65535 sec.
 Type 1 HW watchdog implementation exist in old systems and
 all new systems have type 2 HW watchdog.
 Two types of HW implementation have also different register map.
+Type 3 HW watchdog implementation can exist on all Mellanox systems
+with new programmer logic device.
+It's differentiated by WD capability bit.
+Old systems still have only one main watchdog.
 Mellanox system can have 2 watchdogs: main and auxiliary.
 Main and auxiliary watchdog devices can be enabled together
 on the same system.
@@ -54,3 +63,4 @@  The driver checks during initialization if the previous system reset
 was done by the watchdog. If yes, it makes a notification about this event.
 Access to HW registers is performed through a generic regmap interface.
+Programmable logic device registers have little-endian order.