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[216.31.210.19]) by mx.google.com with ESMTP id l8si12287146qey.66.2013.11.18.10.55.27 for ; Mon, 18 Nov 2013 10:55:28 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of tkryger@broadcom.com designates 216.31.210.19 as permitted sender) client-ip=216.31.210.19; Received: from [10.9.208.57] by mms3.broadcom.com with ESMTP (Broadcom SMTP Relay (Email Firewall v6.5)); Mon, 18 Nov 2013 10:54:26 -0800 X-Server-Uuid: B86B6450-0931-4310-942E-F00ED04CA7AF Received: from IRVEXCHSMTP2.corp.ad.broadcom.com (10.9.207.52) by IRVEXCHCAS08.corp.ad.broadcom.com (10.9.208.57) with Microsoft SMTP Server (TLS) id 14.1.438.0; Mon, 18 Nov 2013 10:55:19 -0800 Received: from mail-sj1-12.sj.broadcom.com (10.10.10.20) by IRVEXCHSMTP2.corp.ad.broadcom.com (10.9.207.52) with Microsoft SMTP Server id 14.1.438.0; Mon, 18 Nov 2013 10:55:19 -0800 Received: from mps-infra-lab3.broadcom.com ( mps-infra-lab3.sj.broadcom.com [10.19.114.109]) by mail-sj1-12.sj.broadcom.com (Postfix) with ESMTP id 49EC6207CF; Mon, 18 Nov 2013 10:55:18 -0800 (PST) Received: by mps-infra-lab3.broadcom.com (Postfix, from userid 1004) id 359424589FF; Mon, 18 Nov 2013 10:55:18 -0800 (PST) From: "Tim Kryger" To: "Thierry Reding" , "Rob Herring" , "Pawel Moll" , "Mark Rutland" , "Stephen Warren" , "Ian Campbell" , "Rob Landley" , "Christian Daudt" , "Grant Likely" cc: "Tim Kryger" , "Linux PWM List" , "Device Tree List" , "Linux Doc List" , "Linux Kernel Mailing List" , "Broadcom Kernel Feedback List" , "Linux ARM Kernel List" , "Linaro Patches List" Subject: [PATCH 2/5] pwm: kona: Introduce Kona PWM controller support Date: Mon, 18 Nov 2013 10:54:58 -0800 Message-ID: <1384800901-21711-3-git-send-email-tim.kryger@linaro.org> X-Mailer: git-send-email 1.8.0.1 In-Reply-To: <1384800901-21711-1-git-send-email-tim.kryger@linaro.org> References: <1384800901-21711-1-git-send-email-tim.kryger@linaro.org> MIME-Version: 1.0 X-WSS-ID: 7E94BDE81SC9038038-01-01 X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: tim.kryger@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.128.178 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Add support for the six-channel Kona PWM controller found on Broadcom mobile SoCs like bcm281xx. Signed-off-by: Tim Kryger Reviewed-by: Alex Elder Reviewed-by: Markus Mayer --- drivers/pwm/Kconfig | 10 ++ drivers/pwm/Makefile | 1 + drivers/pwm/pwm-bcm-kona.c | 226 +++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 237 insertions(+) create mode 100644 drivers/pwm/pwm-bcm-kona.c diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index 75840b5..4ed5d8b 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -53,6 +53,16 @@ config PWM_ATMEL_TCB To compile this driver as a module, choose M here: the module will be called pwm-atmel-tcb. +config PWM_BCM_KONA + tristate "Kona PWM support" + depends on ARCH_BCM_MOBILE + default y + help + Generic PWM framework driver for Broadcom Kona PWM block. + + To compile this driver as a module, choose M here: the module + will be called pwm-bcm-kona. + config PWM_BFIN tristate "Blackfin PWM support" depends on BFIN_GPTIMERS diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile index 77a8c18..dd96938 100644 --- a/drivers/pwm/Makefile +++ b/drivers/pwm/Makefile @@ -3,6 +3,7 @@ obj-$(CONFIG_PWM_SYSFS) += sysfs.o obj-$(CONFIG_PWM_AB8500) += pwm-ab8500.o obj-$(CONFIG_PWM_ATMEL_TCB) += pwm-atmel-tcb.o obj-$(CONFIG_PWM_BFIN) += pwm-bfin.o +obj-$(CONFIG_PWM_BCM_KONA) += pwm-bcm-kona.o obj-$(CONFIG_PWM_IMX) += pwm-imx.o obj-$(CONFIG_PWM_JZ4740) += pwm-jz4740.o obj-$(CONFIG_PWM_LPC32XX) += pwm-lpc32xx.o diff --git a/drivers/pwm/pwm-bcm-kona.c b/drivers/pwm/pwm-bcm-kona.c new file mode 100644 index 0000000..cdf30d9 --- /dev/null +++ b/drivers/pwm/pwm-bcm-kona.c @@ -0,0 +1,226 @@ +/* + * Copyright (C) 2013 Broadcom Corporation + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define KONA_PWM_CHANNEL_CNT 6 + +#define PWM_CONTROL_OFFSET (0x00000000) +#define PWM_CONTROL_INITIAL (0x3f3f3f00) +#define PWMOUT_POLARITY(chan) (0x1 << (8 + chan)) +#define PWMOUT_ENABLE(chan) (0x1 << chan) + +#define PRESCALE_OFFSET (0x00000004) +#define PRESCALE_SHIFT(chan) (chan << 2) +#define PRESCALE_MASK(chan) (~(0x7 << (chan << 2))) +#define PRESCALE_MIN (0x00000000) +#define PRESCALE_MAX (0x00000007) + +#define PERIOD_COUNT_OFFSET(chan) (0x00000008 + (chan << 3)) +#define PERIOD_COUNT_MIN (0x00000002) +#define PERIOD_COUNT_MAX (0x00ffffff) + +#define DUTY_CYCLE_HIGH_OFFSET(chan) (0x0000000c + (chan << 3)) +#define DUTY_CYCLE_HIGH_MIN (0x00000000) +#define DUTY_CYCLE_HIGH_MAX (0x00ffffff) + +struct kona_pwmc { + struct pwm_chip chip; + void __iomem *base; + struct clk *clk; +}; + +static void kona_pwmc_apply_settings(struct kona_pwmc *kp, int chan) +{ + /* New settings take effect on rising edge of enable bit */ + writel(readl(kp->base + PWM_CONTROL_OFFSET) & ~PWMOUT_ENABLE(chan), + kp->base + PWM_CONTROL_OFFSET); + writel(readl(kp->base + PWM_CONTROL_OFFSET) | PWMOUT_ENABLE(chan), + kp->base + PWM_CONTROL_OFFSET); +} + +static int kona_pwmc_config(struct pwm_chip *chip, struct pwm_device *pwm, + int duty_ns, int period_ns) +{ + struct kona_pwmc *kp = dev_get_drvdata(chip->dev); + u64 val, div, clk_rate; + unsigned long prescale = PRESCALE_MIN, pc, dc; + int chan = pwm->hwpwm; + + /* + * Find period count, duty count and prescale to suit duty_ns and + * period_ns. This is done according to formulas described below: + * + * period_ns = 10^9 * (PRESCALE + 1) * PC / PWM_CLK_RATE + * duty_ns = 10^9 * (PRESCALE + 1) * DC / PWM_CLK_RATE + * + * PC = (PWM_CLK_RATE * period_ns) / (10^9 * (PRESCALE + 1)) + * DC = (PWM_CLK_RATE * duty_ns) / (10^9 * (PRESCALE + 1)) + */ + + clk_rate = clk_get_rate(kp->clk); + while (1) { + div = 1000000000; + div *= 1 + prescale; + val = clk_rate * period_ns; + pc = div64_u64(val, div); + val = clk_rate * duty_ns; + dc = div64_u64(val, div); + + /* If duty_ns or period_ns are not achievable then return */ + if (pc < PERIOD_COUNT_MIN || dc < DUTY_CYCLE_HIGH_MIN) + return -EINVAL; + + /* + * If pc or dc have crossed their upper limit, then increase + * prescale and recalculate pc and dc. + */ + if (pc > PERIOD_COUNT_MAX || dc > DUTY_CYCLE_HIGH_MAX) { + if (++prescale > PRESCALE_MAX) + return -EINVAL; + continue; + } + break; + } + + /* Program prescale */ + writel((readl(kp->base + PRESCALE_OFFSET) & PRESCALE_MASK(chan)) | + prescale << PRESCALE_SHIFT(chan), + kp->base + PRESCALE_OFFSET); + + /* Program period count */ + writel(pc, kp->base + PERIOD_COUNT_OFFSET(chan)); + + /* Program duty cycle high count */ + writel(dc, kp->base + DUTY_CYCLE_HIGH_OFFSET(chan)); + + if (test_bit(PWMF_ENABLED, &pwm->flags)) + kona_pwmc_apply_settings(kp, chan); + + return 0; +} + +static int kona_pwmc_enable(struct pwm_chip *chip, struct pwm_device *pwm) +{ + return kona_pwmc_config(chip, pwm, pwm->duty_cycle, pwm->period); +} + +static void kona_pwmc_disable(struct pwm_chip *chip, struct pwm_device *pwm) +{ + struct kona_pwmc *kp = dev_get_drvdata(chip->dev); + int chan = pwm->hwpwm; + + /* + * The PWM hardware lacks a proper way to be disabled so + * we just program zero duty cycle high count instead + */ + + writel(0, kp->base + DUTY_CYCLE_HIGH_OFFSET(chan)); + kona_pwmc_apply_settings(kp, chan); +} + +static const struct pwm_ops kona_pwm_ops = { + .config = kona_pwmc_config, + .owner = THIS_MODULE, + .enable = kona_pwmc_enable, + .disable = kona_pwmc_disable, +}; + +static int kona_pwmc_probe(struct platform_device *pdev) +{ + struct kona_pwmc *kp; + struct resource *res; + int ret = 0; + + dev_dbg(&pdev->dev, "bcm_kona_pwmc probe\n"); + + kp = devm_kzalloc(&pdev->dev, sizeof(*kp), GFP_KERNEL); + if (kp == NULL) + return -ENOMEM; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + kp->base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(kp->base)) + return PTR_ERR(kp->base); + + kp->clk = devm_clk_get(&pdev->dev, NULL); + if (IS_ERR(kp->clk)) { + dev_err(&pdev->dev, "Clock get failed : Err %d\n", ret); + return PTR_ERR(kp->clk); + } + + ret = clk_prepare_enable(kp->clk); + if (ret < 0) + return ret; + + /* Set smooth mode, push/pull, and normal polarity for all channels */ + writel(PWM_CONTROL_INITIAL, kp->base + PWM_CONTROL_OFFSET); + + dev_set_drvdata(&pdev->dev, kp); + + kp->chip.dev = &pdev->dev; + kp->chip.ops = &kona_pwm_ops; + kp->chip.base = -1; + kp->chip.npwm = KONA_PWM_CHANNEL_CNT; + + ret = pwmchip_add(&kp->chip); + if (ret < 0) { + clk_disable_unprepare(kp->clk); + dev_err(&pdev->dev, "pwmchip_add() failed: Err %d\n", ret); + } + + return ret; +} + +static int kona_pwmc_remove(struct platform_device *pdev) +{ + struct kona_pwmc *kp = platform_get_drvdata(pdev); + + clk_disable_unprepare(kp->clk); + return pwmchip_remove(&kp->chip); +} + +static const struct of_device_id bcm_kona_pwmc_dt[] = { + {.compatible = "brcm,kona-pwm"}, + {}, +}; +MODULE_DEVICE_TABLE(of, bcm_kona_pwmc_dt); + +static struct platform_driver kona_pwmc_driver = { + + .driver = { + .name = "bcm-kona-pwm", + .owner = THIS_MODULE, + .of_match_table = bcm_kona_pwmc_dt, + }, + + .probe = kona_pwmc_probe, + .remove = kona_pwmc_remove, +}; + +module_platform_driver(kona_pwmc_driver); + +MODULE_AUTHOR("Broadcom"); +MODULE_DESCRIPTION("Driver for KONA PWMC"); +MODULE_LICENSE("GPL"); +MODULE_VERSION("1.0");