diff mbox

[9/9] target-arm: Add AArch32 SIMD VRINTA, VRINTN, VRINTP and VRINTM

Message ID 1389717790-30860-10-git-send-email-will.newton@linaro.org
State Superseded
Headers show

Commit Message

Will Newton Jan. 14, 2014, 4:43 p.m. UTC 
Add support for the AArch32 Advanced SIMD VRINTA, VRINTN, VRINTP
and VRINTM instructions.

Signed-off-by: Will Newton <will.newton@linaro.org>
---
 target-arm/translate.c | 29 ++++++++++++++++++++++++++++-
 1 file changed, 28 insertions(+), 1 deletion(-)

Comments

Peter Maydell Jan. 27, 2014, 4:52 p.m. UTC | #1 
On 14 January 2014 16:43, Will Newton <will.newton@linaro.org> wrote:
> Add support for the AArch32 Advanced SIMD VRINTA, VRINTN, VRINTP
> and VRINTM instructions.

> +                        case NEON_2RM_VRINTN:
> +                        case NEON_2RM_VRINTA:
> +                        case NEON_2RM_VRINTM:
> +                        case NEON_2RM_VRINTP:
> +                        {
> +                            TCGv_i32 tcg_rmode;
> +                            TCGv_ptr fpstatus = get_fpstatus_ptr(1);
> +                            int rmode = fp_decode_rm[((op & 0x6) >> 1) ^ 1];
> +                            tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode));
> +                            gen_helper_set_neon_rmode(tcg_rmode, tcg_rmode,
> +                                                      cpu_env);
> +                            gen_helper_rints(cpu_F0s, cpu_F0s, fpstatus);
> +                            gen_helper_set_neon_rmode(tcg_rmode, tcg_rmode,
> +                                                      cpu_env);
> +                            tcg_temp_free_ptr(fpstatus);
> +                            tcg_temp_free_i32(tcg_rmode);
> +                            break;

This is almost exactly the same as the VRINTZ case so I think
it would be nicer to combine them:
    if (op == NEON_2RM_VRINTZ) {
        rmode = FPROUNDING_ZERO;
    } else {
        rmode = fp_decode_rm[...];
    }

&c.

thanks
-- PMM
diff mbox

Patch

diff --git a/target-arm/translate.c b/target-arm/translate.c
index 16242d3..5564cb9 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -4709,10 +4709,14 @@  static const uint8_t neon_3r_sizes[] = {
 #define NEON_2RM_VMOVN 36 /* Includes VQMOVN, VQMOVUN */
 #define NEON_2RM_VQMOVN 37 /* Includes VQMOVUN */
 #define NEON_2RM_VSHLL 38
+#define NEON_2RM_VRINTN 40
 #define NEON_2RM_VRINTX 41
+#define NEON_2RM_VRINTA 42
 #define NEON_2RM_VRINTZ 43
 #define NEON_2RM_VCVT_F16_F32 44
+#define NEON_2RM_VRINTM 45
 #define NEON_2RM_VCVT_F32_F16 46
+#define NEON_2RM_VRINTP 47
 #define NEON_2RM_VRECPE 56
 #define NEON_2RM_VRSQRTE 57
 #define NEON_2RM_VRECPE_F 58
@@ -4726,7 +4730,8 @@  static int neon_2rm_is_float_op(int op)
 {
     /* Return true if this neon 2reg-misc op is float-to-float */
     return (op == NEON_2RM_VABS_F || op == NEON_2RM_VNEG_F ||
-            op == NEON_2RM_VRINTX || op == NEON_2RM_VRINTZ ||
+            (op >= NEON_2RM_VRINTN && op <= NEON_2RM_VRINTZ) ||
+            op == NEON_2RM_VRINTM || op == NEON_2RM_VRINTP ||
             op >= NEON_2RM_VRECPE_F);
 }
 
@@ -4771,10 +4776,14 @@  static const uint8_t neon_2rm_sizes[] = {
     [NEON_2RM_VMOVN] = 0x7,
     [NEON_2RM_VQMOVN] = 0x7,
     [NEON_2RM_VSHLL] = 0x7,
+    [NEON_2RM_VRINTN] = 0x4,
     [NEON_2RM_VRINTX] = 0x4,
+    [NEON_2RM_VRINTA] = 0x4,
     [NEON_2RM_VRINTZ] = 0x4,
     [NEON_2RM_VCVT_F16_F32] = 0x2,
+    [NEON_2RM_VRINTM] = 0x4,
     [NEON_2RM_VCVT_F32_F16] = 0x2,
+    [NEON_2RM_VRINTP] = 0x4,
     [NEON_2RM_VRECPE] = 0x4,
     [NEON_2RM_VRSQRTE] = 0x4,
     [NEON_2RM_VRECPE_F] = 0x4,
@@ -6485,6 +6494,24 @@  static int disas_neon_data_insn(CPUARMState * env, DisasContext *s, uint32_t ins
                             }
                             neon_store_reg(rm, pass, tmp2);
                             break;
+                        case NEON_2RM_VRINTN:
+                        case NEON_2RM_VRINTA:
+                        case NEON_2RM_VRINTM:
+                        case NEON_2RM_VRINTP:
+                        {
+                            TCGv_i32 tcg_rmode;
+                            TCGv_ptr fpstatus = get_fpstatus_ptr(1);
+                            int rmode = fp_decode_rm[((op & 0x6) >> 1) ^ 1];
+                            tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode));
+                            gen_helper_set_neon_rmode(tcg_rmode, tcg_rmode,
+                                                      cpu_env);
+                            gen_helper_rints(cpu_F0s, cpu_F0s, fpstatus);
+                            gen_helper_set_neon_rmode(tcg_rmode, tcg_rmode,
+                                                      cpu_env);
+                            tcg_temp_free_ptr(fpstatus);
+                            tcg_temp_free_i32(tcg_rmode);
+                            break;
+                        }
                         case NEON_2RM_VRINTX:
                         {
                             TCGv_ptr fpstatus = get_fpstatus_ptr(1);