diff mbox

gas: ARM: Fix encoding of VCVTr.s32.f64 instructions

Message ID 1389867216-7020-1-git-send-email-will.newton@linaro.org
State Accepted
Headers show

Commit Message

Will Newton Jan. 16, 2014, 10:13 a.m. UTC 
The direct rounding floating-point VCVT instructions introduced in
ARMv8 encode the s32.f64 variant incorrectly. The op bit should be
set to 1 for all signed conversions.

gas/ChangeLog:

2014-01-16  Will Newton  <will.newton@linaro.org>

	* config/tc-arm.c (do_vfp_nsyn_cvt_fpv8): Set OP to 1
	for the s32.f64 flavours of VCVT.

gas/testsuite/ChangeLog:

2014-01-16  Will Newton  <will.newton@linaro.org>

	* gas/arm/armv8-a+fp.d: Correct encoding of vcvta.s32.f64.
---
 gas/config/tc-arm.c                | 2 +-
 gas/testsuite/gas/arm/armv8-a+fp.d | 8 ++++----
 2 files changed, 5 insertions(+), 5 deletions(-)

Comments

Will Newton Jan. 20, 2014, 1:40 p.m. UTC | #1 
On 17 January 2014 15:05, Richard Earnshaw <rearnsha@arm.com> wrote:
> On 16/01/14 10:13, Will Newton wrote:
>> The direct rounding floating-point VCVT instructions introduced in
>> ARMv8 encode the s32.f64 variant incorrectly. The op bit should be
>> set to 1 for all signed conversions.
>>
>> gas/ChangeLog:
>>
>> 2014-01-16  Will Newton  <will.newton@linaro.org>
>>
>>       * config/tc-arm.c (do_vfp_nsyn_cvt_fpv8): Set OP to 1
>>       for the s32.f64 flavours of VCVT.
>>
>
> OK.

Is this ok for the 2.24 branch too?

Thanks,
diff mbox

Patch

diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index 08b5ea2..e596217 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -14671,7 +14671,7 @@  do_vfp_nsyn_cvt_fpv8 (enum neon_cvt_flavour flavour,
     {
     case neon_cvt_flavour_s32_f64:
       sz = 1;
-      op = 0;
+      op = 1;
       break;
     case neon_cvt_flavour_s32_f32:
       sz = 0;
diff --git a/gas/testsuite/gas/arm/armv8-a+fp.d b/gas/testsuite/gas/arm/armv8-a+fp.d
index d50a73b..6443c4b 100644
--- a/gas/testsuite/gas/arm/armv8-a+fp.d
+++ b/gas/testsuite/gas/arm/armv8-a+fp.d
@@ -32,8 +32,8 @@  Disassembly of section .text:
 0[0-9a-f]+ <[^>]+> fefd0ae0 	vcvtn.s32.f32	s1, s1
 0[0-9a-f]+ <[^>]+> febefa4f 	vcvtp.u32.f32	s30, s30
 0[0-9a-f]+ <[^>]+> fefffa6f 	vcvtm.u32.f32	s31, s31
-0[0-9a-f]+ <[^>]+> febc0b40 	vcvta.u32.f64	s0, d0
-0[0-9a-f]+ <[^>]+> fefd0b60 	vcvtn.u32.f64	s1, d16
+0[0-9a-f]+ <[^>]+> febc0bc0 	vcvta.s32.f64	s0, d0
+0[0-9a-f]+ <[^>]+> fefd0be0 	vcvtn.s32.f64	s1, d16
 0[0-9a-f]+ <[^>]+> febefb4f 	vcvtp.u32.f64	s30, d15
 0[0-9a-f]+ <[^>]+> fefffb6f 	vcvtm.u32.f64	s31, d31
 0[0-9a-f]+ <[^>]+> eeb60ac0 	vrintz.f32	s0, s0
@@ -86,8 +86,8 @@  Disassembly of section .text:
 0[0-9a-f]+ <[^>]+> fefd 0ae0 	vcvtn.s32.f32	s1, s1
 0[0-9a-f]+ <[^>]+> febe fa4f 	vcvtp.u32.f32	s30, s30
 0[0-9a-f]+ <[^>]+> feff fa6f 	vcvtm.u32.f32	s31, s31
-0[0-9a-f]+ <[^>]+> febc 0b40 	vcvta.u32.f64	s0, d0
-0[0-9a-f]+ <[^>]+> fefd 0b60 	vcvtn.u32.f64	s1, d16
+0[0-9a-f]+ <[^>]+> febc 0bc0 	vcvta.s32.f64	s0, d0
+0[0-9a-f]+ <[^>]+> fefd 0be0 	vcvtn.s32.f64	s1, d16
 0[0-9a-f]+ <[^>]+> febe fb4f 	vcvtp.u32.f64	s30, d15
 0[0-9a-f]+ <[^>]+> feff fb6f 	vcvtm.u32.f64	s31, d31
 0[0-9a-f]+ <[^>]+> eeb6 0ac0 	vrintz.f32	s0, s0