From patchwork Fri Jul 10 16:21:37 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hemant Agrawal X-Patchwork-Id: 235255 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp603155ilg; Fri, 10 Jul 2020 09:27:08 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxeIxdH1KahXP5sKIuJkPNq653vuIAjH9WvmPev7xE4/Q97TAa0/iuZ38+9PONkySH64Pvl X-Received: by 2002:a50:fd07:: with SMTP id i7mr44075215eds.221.1594398428525; Fri, 10 Jul 2020 09:27:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1594398428; cv=none; d=google.com; s=arc-20160816; b=uv8x9kXrphzbbYOAXGzmjB+yNfqkO2FzkAZF7odPuP0YCPiJ3jwLAY31twkG4AeZ2x Ye4VSXDXXj15DrmQdu7HkCT5Dn8x/Kkz6uJT6I37f2hbUj/qqyEtWMs3+xL/rri8wtUf tkzlSMCjKwdXcDf2Of2UiJJB5rxAIQJw/FzgbEe6wKa5GDZZXyNR4LAfjLG/bcVlFt1Q IZb+NUF5qkGve/Cxn5Upz4H14oPzX56BbxdVZfw0+/Gz9h23DJakBqqePEWjWSopEKaC VeHcfZMys1wLrtz6g4U67T8YGpPqujUqgwhQlLyyi76m12XdgGaA5Q6NlLkbhG5dMSrF 8klA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:cc:to:from; bh=hHvzswPG1OmMlNGZyjsUI/UzIidnwZu1FhhilW8vQ70=; b=jpetsLoPcb5fn38DXSSyCttfzYMneNbmvSHx5kPtlydB9qFLXWVDnxD0F5Bn1A3qvG 5OJTGScrt/I/UmCRpqVUkupyVbe9fGdpabV95JjzfRCnI1tBGXMVPUhOWNSKitAeCsHP V6YBHLXQmdF1HOKMYqBQBG1IMZsgw4H9emwU9Jfzd3GUOca5RMWEGRjXprzzt3/csghI JrJRbzhshnpTNfj3Ok9tQq67OI7hPedJpOCVwrZVabmUD15UAii1FF2Krb1fMSHsP98d qfYFamx1sG1KCymH2r3j041nGvQJnqB5N+TW739+WvbQTFMrVJwxsb1Q6K1B24BjMNEf K/DQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of dev-bounces@dpdk.org designates 92.243.14.124 as permitted sender) smtp.mailfrom=dev-bounces@dpdk.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nxp.com Return-Path: Received: from dpdk.org (dpdk.org. [92.243.14.124]) by mx.google.com with ESMTP id b24si4057592edw.188.2020.07.10.09.27.08; Fri, 10 Jul 2020 09:27:08 -0700 (PDT) Received-SPF: pass (google.com: domain of dev-bounces@dpdk.org designates 92.243.14.124 as permitted sender) client-ip=92.243.14.124; Authentication-Results: mx.google.com; spf=pass (google.com: domain of dev-bounces@dpdk.org designates 92.243.14.124 as permitted sender) smtp.mailfrom=dev-bounces@dpdk.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nxp.com Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 8B2561DD43; Fri, 10 Jul 2020 18:26:10 +0200 (CEST) Received: from inva020.nxp.com (inva020.nxp.com [92.121.34.13]) by dpdk.org (Postfix) with ESMTP id 984BD1DA05 for ; Fri, 10 Jul 2020 18:26:01 +0200 (CEST) Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 76C2E1A04AF; Fri, 10 Jul 2020 18:26:01 +0200 (CEST) Received: from invc005.ap-rdc01.nxp.com (invc005.ap-rdc01.nxp.com [165.114.16.14]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 937E51A04BF; Fri, 10 Jul 2020 18:25:59 +0200 (CEST) Received: from bf-netperf1.ap.freescale.net (bf-netperf1.ap.freescale.net [10.232.133.63]) by invc005.ap-rdc01.nxp.com (Postfix) with ESMTP id 6426540305; Sat, 11 Jul 2020 00:25:57 +0800 (SGT) From: Hemant Agrawal To: dev@dpdk.org Cc: ferruh.yigit@intel.com, Hemant Agrawal Date: Fri, 10 Jul 2020 21:51:37 +0530 Message-Id: <20200710162137.22973-9-hemant.agrawal@nxp.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200710162137.22973-1-hemant.agrawal@nxp.com> References: <20200710162137.22973-1-hemant.agrawal@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Subject: [dpdk-dev] [PATCH 9/9] net/dpaa: support Rxq and Txq info routines X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This patch add support for rxq_info_get and txq_info_get Signed-off-by: Hemant Agrawal --- drivers/bus/dpaa/include/fsl_qman.h | 3 ++ drivers/net/dpaa/dpaa_ethdev.c | 51 +++++++++++++++++++++++++++-- 2 files changed, 52 insertions(+), 2 deletions(-) -- 2.17.1 diff --git a/drivers/bus/dpaa/include/fsl_qman.h b/drivers/bus/dpaa/include/fsl_qman.h index 0d9cfc339..8ba37411a 100644 --- a/drivers/bus/dpaa/include/fsl_qman.h +++ b/drivers/bus/dpaa/include/fsl_qman.h @@ -1251,6 +1251,9 @@ struct qman_fq { void **qman_fq_lookup_table; u32 key; #endif + u16 nb_desc; + u16 resv; + u64 offloads; }; /* diff --git a/drivers/net/dpaa/dpaa_ethdev.c b/drivers/net/dpaa/dpaa_ethdev.c index ea178f4d4..c15e2b546 100644 --- a/drivers/net/dpaa/dpaa_ethdev.c +++ b/drivers/net/dpaa/dpaa_ethdev.c @@ -748,6 +748,8 @@ int dpaa_eth_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, DPAA_PMD_ERR("%p:Rx deferred start not supported", (void *)dev); return -EINVAL; } + rxq->nb_desc = UINT16_MAX; + rxq->offloads = rx_conf->offloads; DPAA_PMD_INFO("Rx queue setup for queue index: %d fq_id (0x%x)", queue_idx, rxq->fqid); @@ -895,6 +897,7 @@ int dpaa_eth_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, if (dpaa_intf->cgr_rx) { struct qm_mcc_initcgr cgr_opts = {0}; + rxq->nb_desc = nb_desc; /* Enable tail drop with cgr on this queue */ qm_cgr_cs_thres_set64(&cgr_opts.cgr.cs_thres, nb_desc, 0); ret = qman_modify_cgr(dpaa_intf->cgr_rx, 0, &cgr_opts); @@ -1015,6 +1018,7 @@ int dpaa_eth_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, const struct rte_eth_txconf *tx_conf) { struct dpaa_if *dpaa_intf = dev->data->dev_private; + struct qman_fq *txq = &dpaa_intf->tx_queues[queue_idx]; PMD_INIT_FUNC_TRACE(); @@ -1023,6 +1027,9 @@ int dpaa_eth_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, DPAA_PMD_ERR("%p:Tx deferred start not supported", (void *)dev); return -EINVAL; } + txq->nb_desc = UINT16_MAX; + txq->offloads = tx_conf->offloads; + if (queue_idx >= dev->data->nb_tx_queues) { rte_errno = EOVERFLOW; DPAA_PMD_ERR("%p: queue index out of range (%u >= %u)", @@ -1031,8 +1038,8 @@ int dpaa_eth_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, } DPAA_PMD_INFO("Tx queue setup for queue index: %d fq_id (0x%x)", - queue_idx, dpaa_intf->tx_queues[queue_idx].fqid); - dev->data->tx_queues[queue_idx] = &dpaa_intf->tx_queues[queue_idx]; + queue_idx, txq->fqid); + dev->data->tx_queues[queue_idx] = txq; return 0; } @@ -1247,6 +1254,43 @@ static int dpaa_dev_queue_intr_disable(struct rte_eth_dev *dev, return 0; } +static void +dpaa_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, + struct rte_eth_rxq_info *qinfo) +{ + struct dpaa_if *dpaa_intf = dev->data->dev_private; + struct qman_fq *rxq; + + rxq = dev->data->rx_queues[queue_id]; + + qinfo->mp = dpaa_intf->bp_info->mp; + qinfo->scattered_rx = dev->data->scattered_rx; + qinfo->nb_desc = rxq->nb_desc; + qinfo->conf.rx_free_thresh = 1; + qinfo->conf.rx_drop_en = 1; + qinfo->conf.rx_deferred_start = 0; + qinfo->conf.offloads = rxq->offloads; +} + +static void +dpaa_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, + struct rte_eth_txq_info *qinfo) +{ + struct qman_fq *txq; + + txq = dev->data->tx_queues[queue_id]; + + qinfo->nb_desc = txq->nb_desc; + qinfo->conf.tx_thresh.pthresh = 0; + qinfo->conf.tx_thresh.hthresh = 0; + qinfo->conf.tx_thresh.wthresh = 0; + + qinfo->conf.tx_free_thresh = 0; + qinfo->conf.tx_rs_thresh = 0; + qinfo->conf.offloads = txq->offloads; + qinfo->conf.tx_deferred_start = 0; +} + static struct eth_dev_ops dpaa_devops = { .dev_configure = dpaa_eth_dev_configure, .dev_start = dpaa_eth_dev_start, @@ -1262,6 +1306,9 @@ static struct eth_dev_ops dpaa_devops = { .rx_queue_count = dpaa_dev_rx_queue_count, .rx_burst_mode_get = dpaa_dev_rx_burst_mode_get, .tx_burst_mode_get = dpaa_dev_tx_burst_mode_get, + .rxq_info_get = dpaa_rxq_info_get, + .txq_info_get = dpaa_txq_info_get, + .flow_ctrl_get = dpaa_flow_ctrl_get, .flow_ctrl_set = dpaa_flow_ctrl_set,