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[104.188.17.28]) by smtp.gmail.com with ESMTPSA id o4sm3707657pjo.16.2020.07.15.22.48.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Jul 2020 22:48:17 -0700 (PDT) From: Bjorn Andersson To: Bjorn Andersson , Ohad Ben-Cohen Cc: linux-arm-msm@vger.kernel.org, linux-remoteproc@vger.kernel.org, linux-kernel@vger.kernel.org, Lee Jones , Nathan Chancellor Subject: [PATCH] remoteproc: qcom: pil-info: Fix shift overflow Date: Wed, 15 Jul 2020 22:48:17 -0700 Message-Id: <20200716054817.157608-1-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.26.2 MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On platforms with 32-bit phys_addr_t the shift to get the upper word of the base address of the memory region is invalid. Cast the base to 64 bit to resolv this. Fixes: 549b67da660d ("remoteproc: qcom: Introduce helper to store pil info in IMEM") Reported-by: Lee Jones Reported-by: Nathan Chancellor Signed-off-by: Bjorn Andersson --- drivers/remoteproc/qcom_pil_info.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.26.2 Tested-by: Nathan Chancellor # build diff --git a/drivers/remoteproc/qcom_pil_info.c b/drivers/remoteproc/qcom_pil_info.c index 0536e3904669..5521c4437ffa 100644 --- a/drivers/remoteproc/qcom_pil_info.c +++ b/drivers/remoteproc/qcom_pil_info.c @@ -108,7 +108,7 @@ int qcom_pil_info_store(const char *image, phys_addr_t base, size_t size) found_existing: /* Use two writel() as base is only aligned to 4 bytes on odd entries */ writel(base, entry + PIL_RELOC_NAME_LEN); - writel(base >> 32, entry + PIL_RELOC_NAME_LEN + 4); + writel((u64)base >> 32, entry + PIL_RELOC_NAME_LEN + 4); writel(size, entry + PIL_RELOC_NAME_LEN + sizeof(__le64)); mutex_unlock(&pil_reloc_lock);