diff mbox series

[v3,12/21] arm: socfpga: Secure register access in PHY mode setup

Message ID 1582264059-37988-13-git-send-email-chee.hong.ang@intel.com
State New
Headers show
Series Enable ARM Trusted Firmware for U-Boot | expand

Commit Message

Ang, Chee Hong Feb. 21, 2020, 5:47 a.m. UTC 
From: Chee Hong Ang <chee.hong.ang at intel.com>

Allow access to System Manager's EMAC control register from
non-secure mode during PHY mode setup.

Signed-off-by: Chee Hong Ang <chee.hong.ang at intel.com>
---
 arch/arm/mach-socfpga/misc_s10.c | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)
diff mbox series

Patch

diff --git a/arch/arm/mach-socfpga/misc_s10.c b/arch/arm/mach-socfpga/misc_s10.c
index adfff82..393b486 100644
--- a/arch/arm/mach-socfpga/misc_s10.c
+++ b/arch/arm/mach-socfpga/misc_s10.c
@@ -18,6 +18,7 @@ 
 #include <asm/pl310.h>
 #include <linux/libfdt.h>
 #include <asm/arch/mailbox_s10.h>
+#include <asm/arch/secure_reg_helper.h>
 
 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
 
@@ -65,9 +66,9 @@  static u32 socfpga_phymode_setup(u32 gmac_index, const char *phymode)
 	else
 		return -EINVAL;
 
-	clrsetbits_le32(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_EMAC0 +
-			gmac_index,
-			SYSMGR_EMACGRP_CTRL_PHYSEL_MASK, modereg);
+	socfpga_secure_reg_update32(socfpga_get_sysmgr_addr() +
+				    SYSMGR_SOC64_EMAC0 + gmac_index,
+				    SYSMGR_EMACGRP_CTRL_PHYSEL_MASK, modereg);
 
 	return 0;
 }