diff mbox series

[v2,2/6] riscv: Merge unnecessary SMP ifdefs in start.S

Message ID 1587049773-1464-3-git-send-email-bmeng.cn@gmail.com
State Accepted
Commit 84dc9d26908798c7e9ee5469965c16653593fde5
Headers show
Series riscv: Make SBI v0.2 the default SBI version to work with OpenSBI v0.7 | expand

Commit Message

Bin Meng April 16, 2020, 3:09 p.m. UTC 
Two consecutive SMP ifdefs blocks can be combined into one.

Signed-off-by: Bin Meng <bmeng.cn at gmail.com>
Reviewed-by: Atish Patra <atish.patra at wdc.com>
---

Changes in v2: None

 arch/riscv/cpu/start.S | 4 ----
 1 file changed, 4 deletions(-)
diff mbox series

Patch

diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index 6b3ff99..ecf0482 100644
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -58,9 +58,7 @@  _start:
 	/* tp: hart id */
 	li	t0, CONFIG_NR_CPUS
 	bge	tp, t0, hart_out_of_bounds_loop
-#endif
 
-#ifdef CONFIG_SMP
 	/* set xSIE bit to receive IPIs */
 #if CONFIG_IS_ENABLED(RISCV_MMODE)
 	li	t0, MIE_MSIE
@@ -377,9 +375,7 @@  hart_out_of_bounds_loop:
 	/* Harts in this loop are out of bounds, increase CONFIG_NR_CPUS. */
 	wfi
 	j	hart_out_of_bounds_loop
-#endif
 
-#ifdef CONFIG_SMP
 /* SMP relocation entry */
 secondary_hart_relocate:
 	/* a1: new sp */