| Message ID | 20200417151209.6185-1-m-karicheri2@ti.com |
|---|---|
| State | Accepted |
| Commit | 39821d58c91d97b48a36ea340adedc4c9b8f5b85 |
| Headers | show |
| Series | net: ethernet: ti: am65-cpsw-nuss: enable 10Mbps link speed in rgmii mode | expand |
+ Lokesh On 04/17/2020 11:12 AM, Murali Karicheri wrote: > In RGMII mode the 10Mbps link speed is supported only when CPSW2G MAC SL is > configured for External Control ("in band") mode > CPSW_PN_MAC_CONTROL_REG.CTL_EN(18) = 1 > > Hence update am65_cpsw_update_link() to follow documentation. > > Signed-off-by: Murali Karicheri <m-karicheri2 at ti.com> > --- > drivers/net/ti/am65-cpsw-nuss.c | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/drivers/net/ti/am65-cpsw-nuss.c b/drivers/net/ti/am65-cpsw-nuss.c > index 2b77213001..7531a07203 100644 > --- a/drivers/net/ti/am65-cpsw-nuss.c > +++ b/drivers/net/ti/am65-cpsw-nuss.c > @@ -61,6 +61,7 @@ > > #define AM65_CPSW_MACSL_CTL_REG 0x0 > #define AM65_CPSW_MACSL_CTL_REG_IFCTL_A BIT(15) > +#define AM65_CPSW_MACSL_CTL_EXT_EN BIT(18) > #define AM65_CPSW_MACSL_CTL_REG_GIG BIT(7) > #define AM65_CPSW_MACSL_CTL_REG_GMII_EN BIT(5) > #define AM65_CPSW_MACSL_CTL_REG_LOOPBACK BIT(1) > @@ -187,6 +188,9 @@ static int am65_cpsw_update_link(struct am65_cpsw_priv *priv) > AM65_CPSW_MACSL_CTL_REG_GMII_EN; > if (phy->speed == 1000) > mac_control |= AM65_CPSW_MACSL_CTL_REG_GIG; > + if (phy->speed == 10 && phy_interface_is_rgmii(phy)) > + /* Can be used with in band mode only */ > + mac_control |= AM65_CPSW_MACSL_CTL_EXT_EN; > if (phy->duplex == DUPLEX_FULL) > mac_control |= AM65_CPSW_MACSL_CTL_REG_FULL_DUPLEX; > if (phy->speed == 100) >
On 20/04/2020 14:10, Murali Karicheri wrote: > + Lokesh > > On 04/17/2020 11:12 AM, Murali Karicheri wrote: >> In RGMII mode the 10Mbps link speed is supported only when CPSW2G MAC SL is >> configured for External Control ("in band") mode >> CPSW_PN_MAC_CONTROL_REG.CTL_EN(18) = 1 >> >> Hence update am65_cpsw_update_link() to follow documentation. >> >> Signed-off-by: Murali Karicheri <m-karicheri2 at ti.com> >> --- >> ? drivers/net/ti/am65-cpsw-nuss.c | 4 ++++ >> ? 1 file changed, 4 insertions(+) >> >> diff --git a/drivers/net/ti/am65-cpsw-nuss.c b/drivers/net/ti/am65-cpsw-nuss.c >> index 2b77213001..7531a07203 100644 >> --- a/drivers/net/ti/am65-cpsw-nuss.c >> +++ b/drivers/net/ti/am65-cpsw-nuss.c >> @@ -61,6 +61,7 @@ >> ? #define AM65_CPSW_MACSL_CTL_REG??????????? 0x0 >> ? #define AM65_CPSW_MACSL_CTL_REG_IFCTL_A??????? BIT(15) >> +#define AM65_CPSW_MACSL_CTL_EXT_EN??????? BIT(18) >> ? #define AM65_CPSW_MACSL_CTL_REG_GIG??????? BIT(7) >> ? #define AM65_CPSW_MACSL_CTL_REG_GMII_EN??????? BIT(5) >> ? #define AM65_CPSW_MACSL_CTL_REG_LOOPBACK??? BIT(1) >> @@ -187,6 +188,9 @@ static int am65_cpsw_update_link(struct am65_cpsw_priv *priv) >> ??????????????????? AM65_CPSW_MACSL_CTL_REG_GMII_EN; >> ????????? if (phy->speed == 1000) >> ????????????? mac_control |= AM65_CPSW_MACSL_CTL_REG_GIG; >> +??????? if (phy->speed == 10 && phy_interface_is_rgmii(phy)) >> +??????????? /* Can be used with in band mode only */ >> +??????????? mac_control |= AM65_CPSW_MACSL_CTL_EXT_EN; >> ????????? if (phy->duplex == DUPLEX_FULL) >> ????????????? mac_control |= AM65_CPSW_MACSL_CTL_REG_FULL_DUPLEX; >> ????????? if (phy->speed == 100) >> > Reviewed-by: Grygorii Strashko <grygorii.strashko at ti.com>
Hi Joe, On 22/04/20 10:00 PM, Grygorii Strashko wrote: > > > On 20/04/2020 14:10, Murali Karicheri wrote: >> + Lokesh >> >> On 04/17/2020 11:12 AM, Murali Karicheri wrote: >>> In RGMII mode the 10Mbps link speed is supported only when CPSW2G MAC SL is >>> configured for External Control ("in band") mode >>> CPSW_PN_MAC_CONTROL_REG.CTL_EN(18) = 1 >>> >>> Hence update am65_cpsw_update_link() to follow documentation. >>> >>> Signed-off-by: Murali Karicheri <m-karicheri2 at ti.com> I see this in my patchworks. Do you want me to pick it up or will you pick it up? Can you provide your review if you want me to pick it up? Thanks and regards, Lokesh
On 20/04/20 4:40 PM, Murali Karicheri wrote: > + Lokesh > > On 04/17/2020 11:12 AM, Murali Karicheri wrote: >> In RGMII mode the 10Mbps link speed is supported only when CPSW2G MAC SL is >> configured for External Control ("in band") mode >> CPSW_PN_MAC_CONTROL_REG.CTL_EN(18) = 1 >> >> Hence update am65_cpsw_update_link() to follow documentation. >> >> Signed-off-by: Murali Karicheri <m-karicheri2 at ti.com> Merged into u-boot-ti. Thanks and regards, Lokesh
diff --git a/drivers/net/ti/am65-cpsw-nuss.c b/drivers/net/ti/am65-cpsw-nuss.c index 2b77213001..7531a07203 100644 --- a/drivers/net/ti/am65-cpsw-nuss.c +++ b/drivers/net/ti/am65-cpsw-nuss.c @@ -61,6 +61,7 @@ #define AM65_CPSW_MACSL_CTL_REG 0x0 #define AM65_CPSW_MACSL_CTL_REG_IFCTL_A BIT(15) +#define AM65_CPSW_MACSL_CTL_EXT_EN BIT(18) #define AM65_CPSW_MACSL_CTL_REG_GIG BIT(7) #define AM65_CPSW_MACSL_CTL_REG_GMII_EN BIT(5) #define AM65_CPSW_MACSL_CTL_REG_LOOPBACK BIT(1) @@ -187,6 +188,9 @@ static int am65_cpsw_update_link(struct am65_cpsw_priv *priv) AM65_CPSW_MACSL_CTL_REG_GMII_EN; if (phy->speed == 1000) mac_control |= AM65_CPSW_MACSL_CTL_REG_GIG; + if (phy->speed == 10 && phy_interface_is_rgmii(phy)) + /* Can be used with in band mode only */ + mac_control |= AM65_CPSW_MACSL_CTL_EXT_EN; if (phy->duplex == DUPLEX_FULL) mac_control |= AM65_CPSW_MACSL_CTL_REG_FULL_DUPLEX; if (phy->speed == 100)
In RGMII mode the 10Mbps link speed is supported only when CPSW2G MAC SL is configured for External Control ("in band") mode CPSW_PN_MAC_CONTROL_REG.CTL_EN(18) = 1 Hence update am65_cpsw_update_link() to follow documentation. Signed-off-by: Murali Karicheri <m-karicheri2 at ti.com> --- drivers/net/ti/am65-cpsw-nuss.c | 4 ++++ 1 file changed, 4 insertions(+)