| Message ID | 20200420045254.5183-1-andy.tang@nxp.com |
|---|---|
| State | Accepted |
| Commit | 35ad8f7af4ec7a2e449322c86c5301c48765a269 |
| Headers | show |
| Series | [v3] armv8: ls1046ardb: update the WRLVL_START to accommodate more DIMM | expand |
>-----Original Message----- >From: U-Boot <u-boot-bounces at lists.denx.de> On Behalf Of Yuantian Tang >Sent: Monday, April 20, 2020 10:23 AM >To: Priyanka Jain <priyanka.jain at nxp.com> >Cc: u-boot at lists.denx.de; Andy Tang <andy.tang at nxp.com> >Subject: [PATCH v3] armv8: ls1046ardb: update the WRLVL_START to >accommodate more DIMM > >The WRLVL_START values are optimized for old DDR MTA18ASF1G72AZ. >Update DDR struct to set new WRLVL_START values so that the new DIMM >MTA18ADF2G72AZ get optimized and the old DIMM still works. > >Signed-off-by: Yuantian Tang <andy.tang at nxp.com> >--- >v3: > - fix typo > board/freescale/ls1046ardb/ddr.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > >diff --git a/board/freescale/ls1046ardb/ddr.h >b/board/freescale/ls1046ardb/ddr.h >index 3b4d44d465..05baef232a 100644 >--- a/board/freescale/ls1046ardb/ddr.h >+++ b/board/freescale/ls1046ardb/ddr.h >@@ -32,7 +32,7 @@ static const struct board_specific_parameters udimm0[] >= { > {2, 1350, 0, 8, 6, 0x0708090B, 0x0C0D0E09,}, > {2, 1666, 0, 8, 7, 0x08090A0C, 0x0D0F100B,}, > {2, 1900, 0, 8, 7, 0x09090B0D, 0x0E10120B,}, >- {2, 2300, 0, 8, 9, 0x0A0B0C10, 0x1213140E,}, >+ {2, 2300, 0, 8, 7, 0x08090A0E, 0x1011120C,}, > {} > }; > >-- >2.17.1 Reviewed-by: Priyanka Jain <priyanka.jain at nxp.com>
>-----Original Message----- >From: U-Boot <u-boot-bounces at lists.denx.de> On Behalf Of Yuantian Tang >Sent: Monday, April 20, 2020 10:23 AM >To: Priyanka Jain <priyanka.jain at nxp.com> >Cc: u-boot at lists.denx.de; Andy Tang <andy.tang at nxp.com> >Subject: [PATCH v3] armv8: ls1046ardb: update the WRLVL_START to >accommodate more DIMM > >The WRLVL_START values are optimized for old DDR MTA18ASF1G72AZ. >Update DDR struct to set new WRLVL_START values so that the new DIMM >MTA18ADF2G72AZ get optimized and the old DIMM still works. > >Signed-off-by: Yuantian Tang <andy.tang at nxp.com> >--- Patch applied to fsl-qoriq after trimming the subject line. Awaiting upstream Thanks Priyanka
diff --git a/board/freescale/ls1046ardb/ddr.h b/board/freescale/ls1046ardb/ddr.h index 3b4d44d465..05baef232a 100644 --- a/board/freescale/ls1046ardb/ddr.h +++ b/board/freescale/ls1046ardb/ddr.h @@ -32,7 +32,7 @@ static const struct board_specific_parameters udimm0[] = { {2, 1350, 0, 8, 6, 0x0708090B, 0x0C0D0E09,}, {2, 1666, 0, 8, 7, 0x08090A0C, 0x0D0F100B,}, {2, 1900, 0, 8, 7, 0x09090B0D, 0x0E10120B,}, - {2, 2300, 0, 8, 9, 0x0A0B0C10, 0x1213140E,}, + {2, 2300, 0, 8, 7, 0x08090A0E, 0x1011120C,}, {} };
The WRLVL_START values are optimized for old DDR MTA18ASF1G72AZ. Update DDR struct to set new WRLVL_START values so that the new DIMM MTA18ADF2G72AZ get optimized and the old DIMM still works. Signed-off-by: Yuantian Tang <andy.tang at nxp.com> --- v3: - fix typo board/freescale/ls1046ardb/ddr.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)