diff mbox series

[3/9] board: st: create common file stpmic1.c

Message ID 20200421171123.3.I68223ba559c92c10a234c74b5589a38df45603c1@changeid
State Superseded
Headers show
Series stm32mp1: use OPP information for PLL1 settings in SPL | expand

Commit Message

Patrick Delaunay April 21, 2020, 3:11 p.m. UTC 
Move function board_ddr_power_init() in a new file stpmic1 in
board/st/common to avoid duplicated code in each board using
stpmic1

Signed-off-by: Patrick Delaunay <patrick.delaunay at st.com>
---

 board/dhelectronics/dh_stm32mp1/Makefile |   2 +-
 board/st/common/Makefile                 |   1 +
 board/st/common/stpmic1.c                | 162 +++++++++++++++++++++++
 board/st/stm32mp1/board.c                | 158 ----------------------
 4 files changed, 164 insertions(+), 159 deletions(-)
 create mode 100644 board/st/common/stpmic1.c

Comments

Patrice CHOTARD May 11, 2020, 1:49 p.m. UTC | #1 
Hi Patrick

On 4/21/20 5:11 PM, Patrick Delaunay wrote:
> Move function board_ddr_power_init() in a new file stpmic1 in
> board/st/common to avoid duplicated code in each board using
> stpmic1
>
> Signed-off-by: Patrick Delaunay <patrick.delaunay at st.com>
> ---
>
>  board/dhelectronics/dh_stm32mp1/Makefile |   2 +-
>  board/st/common/Makefile                 |   1 +
>  board/st/common/stpmic1.c                | 162 +++++++++++++++++++++++
>  board/st/stm32mp1/board.c                | 158 ----------------------
>  4 files changed, 164 insertions(+), 159 deletions(-)
>  create mode 100644 board/st/common/stpmic1.c
>
> diff --git a/board/dhelectronics/dh_stm32mp1/Makefile b/board/dhelectronics/dh_stm32mp1/Makefile
> index b42c4e4c04..04586c0a28 100644
> --- a/board/dhelectronics/dh_stm32mp1/Makefile
> +++ b/board/dhelectronics/dh_stm32mp1/Makefile
> @@ -7,4 +7,4 @@ ifdef CONFIG_SPL_BUILD
>  obj-y += ../../st/stm32mp1/spl.o
>  endif
>  
> -obj-y += ../../st/stm32mp1/board.o board.o
> +obj-y += ../../st/common/stpmic1.o board.o
> diff --git a/board/st/common/Makefile b/board/st/common/Makefile
> index 8553606b90..78bc0307f7 100644
> --- a/board/st/common/Makefile
> +++ b/board/st/common/Makefile
> @@ -4,3 +4,4 @@
>  #
>  
>  obj-$(CONFIG_CMD_STBOARD) += cmd_stboard.o
> +obj-$(CONFIG_PMIC_STPMIC1) += stpmic1.o
> diff --git a/board/st/common/stpmic1.c b/board/st/common/stpmic1.c
> new file mode 100644
> index 0000000000..ca10a2246b
> --- /dev/null
> +++ b/board/st/common/stpmic1.c
> @@ -0,0 +1,162 @@
> +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
> +/*
> + * Copyright (C) 2020, STMicroelectronics - All Rights Reserved
> + */
> +
> +#include <common.h>
> +#include <dm.h>
> +#include <asm/arch/ddr.h>
> +#include <power/pmic.h>
> +#include <power/stpmic1.h>
> +
> +int board_ddr_power_init(enum ddr_type ddr_type)
> +{
> +	struct udevice *dev;
> +	bool buck3_at_1800000v = false;
> +	int ret;
> +	u32 buck2;
> +
> +	ret = uclass_get_device_by_driver(UCLASS_PMIC,
> +					  DM_GET_DRIVER(pmic_stpmic1), &dev);
> +	if (ret)
> +		/* No PMIC on board */
> +		return 0;
> +
> +	switch (ddr_type) {
> +	case STM32MP_DDR3:
> +		/* VTT = Set LDO3 to sync mode */
> +		ret = pmic_reg_read(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3));
> +		if (ret < 0)
> +			return ret;
> +
> +		ret &= ~STPMIC1_LDO3_MODE;
> +		ret &= ~STPMIC1_LDO12356_VOUT_MASK;
> +		ret |= STPMIC1_LDO_VOUT(STPMIC1_LDO3_DDR_SEL);
> +
> +		ret = pmic_reg_write(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3),
> +				     ret);
> +		if (ret < 0)
> +			return ret;
> +
> +		/* VDD_DDR = Set BUCK2 to 1.35V */
> +		ret = pmic_clrsetbits(dev,
> +				      STPMIC1_BUCKX_MAIN_CR(STPMIC1_BUCK2),
> +				      STPMIC1_BUCK_VOUT_MASK,
> +				      STPMIC1_BUCK2_1350000V);
> +		if (ret < 0)
> +			return ret;
> +
> +		/* Enable VDD_DDR = BUCK2 */
> +		ret = pmic_clrsetbits(dev,
> +				      STPMIC1_BUCKX_MAIN_CR(STPMIC1_BUCK2),
> +				      STPMIC1_BUCK_ENA, STPMIC1_BUCK_ENA);
> +		if (ret < 0)
> +			return ret;
> +
> +		mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
> +
> +		/* Enable VREF */
> +		ret = pmic_clrsetbits(dev, STPMIC1_REFDDR_MAIN_CR,
> +				      STPMIC1_VREF_ENA, STPMIC1_VREF_ENA);
> +		if (ret < 0)
> +			return ret;
> +
> +		mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
> +
> +		/* Enable VTT = LDO3 */
> +		ret = pmic_clrsetbits(dev,
> +				      STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3),
> +				      STPMIC1_LDO_ENA, STPMIC1_LDO_ENA);
> +		if (ret < 0)
> +			return ret;
> +
> +		mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
> +
> +		break;
> +
> +	case STM32MP_LPDDR2_16:
> +	case STM32MP_LPDDR2_32:
> +	case STM32MP_LPDDR3_16:
> +	case STM32MP_LPDDR3_32:
> +		/*
> +		 * configure VDD_DDR1 = LDO3
> +		 * Set LDO3 to 1.8V
> +		 * + bypass mode if BUCK3 = 1.8V
> +		 * + normal mode if BUCK3 != 1.8V
> +		 */
> +		ret = pmic_reg_read(dev,
> +				    STPMIC1_BUCKX_MAIN_CR(STPMIC1_BUCK3));
> +		if (ret < 0)
> +			return ret;
> +
> +		if ((ret & STPMIC1_BUCK3_1800000V) == STPMIC1_BUCK3_1800000V)
> +			buck3_at_1800000v = true;
> +
> +		ret = pmic_reg_read(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3));
> +		if (ret < 0)
> +			return ret;
> +
> +		ret &= ~STPMIC1_LDO3_MODE;
> +		ret &= ~STPMIC1_LDO12356_VOUT_MASK;
> +		ret |= STPMIC1_LDO3_1800000;
> +		if (buck3_at_1800000v)
> +			ret |= STPMIC1_LDO3_MODE;
> +
> +		ret = pmic_reg_write(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3),
> +				     ret);
> +		if (ret < 0)
> +			return ret;
> +
> +		/* VDD_DDR2 : Set BUCK2 to 1.2V (16bits) or 1.25V (32 bits)*/
> +		switch (ddr_type) {
> +		case STM32MP_LPDDR2_32:
> +		case STM32MP_LPDDR3_32:
> +			buck2 = STPMIC1_BUCK2_1250000V;
> +			break;
> +		default:
> +		case STM32MP_LPDDR2_16:
> +		case STM32MP_LPDDR3_16:
> +			buck2 = STPMIC1_BUCK2_1200000V;
> +			break;
> +		}
> +
> +		ret = pmic_clrsetbits(dev,
> +				      STPMIC1_BUCKX_MAIN_CR(STPMIC1_BUCK2),
> +				      STPMIC1_BUCK_VOUT_MASK,
> +				      buck2);
> +		if (ret < 0)
> +			return ret;
> +
> +		/* Enable VDD_DDR1 = LDO3 */
> +		ret = pmic_clrsetbits(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3),
> +				      STPMIC1_LDO_ENA, STPMIC1_LDO_ENA);
> +		if (ret < 0)
> +			return ret;
> +
> +		mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
> +
> +		/* Enable VDD_DDR2 =BUCK2 */
> +		ret = pmic_clrsetbits(dev,
> +				      STPMIC1_BUCKX_MAIN_CR(STPMIC1_BUCK2),
> +				      STPMIC1_BUCK_ENA, STPMIC1_BUCK_ENA);
> +		if (ret < 0)
> +			return ret;
> +
> +		mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
> +
> +		/* Enable VREF */
> +		ret = pmic_clrsetbits(dev, STPMIC1_REFDDR_MAIN_CR,
> +				      STPMIC1_VREF_ENA, STPMIC1_VREF_ENA);
> +		if (ret < 0)
> +			return ret;
> +
> +		mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
> +
> +		break;
> +
> +	default:
> +		break;
> +	};
> +
> +	return 0;
> +}
> diff --git a/board/st/stm32mp1/board.c b/board/st/stm32mp1/board.c
> index 4e35d36c76..1887941e57 100644
> --- a/board/st/stm32mp1/board.c
> +++ b/board/st/stm32mp1/board.c
> @@ -4,11 +4,7 @@
>   */
>  
>  #include <common.h>
> -#include <dm.h>
>  #include <asm/io.h>
> -#include <asm/arch/ddr.h>
> -#include <power/pmic.h>
> -#include <power/stpmic1.h>
>  
>  #ifdef CONFIG_DEBUG_UART_BOARD_INIT
>  void board_debug_uart_init(void)
> @@ -36,157 +32,3 @@ void board_debug_uart_init(void)
>  #endif
>  }
>  #endif
> -
> -#ifdef CONFIG_PMIC_STPMIC1
> -int board_ddr_power_init(enum ddr_type ddr_type)
> -{
> -	struct udevice *dev;
> -	bool buck3_at_1800000v = false;
> -	int ret;
> -	u32 buck2;
> -
> -	ret = uclass_get_device_by_driver(UCLASS_PMIC,
> -					  DM_GET_DRIVER(pmic_stpmic1), &dev);
> -	if (ret)
> -		/* No PMIC on board */
> -		return 0;
> -
> -	switch (ddr_type) {
> -	case STM32MP_DDR3:
> -		/* VTT = Set LDO3 to sync mode */
> -		ret = pmic_reg_read(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3));
> -		if (ret < 0)
> -			return ret;
> -
> -		ret &= ~STPMIC1_LDO3_MODE;
> -		ret &= ~STPMIC1_LDO12356_VOUT_MASK;
> -		ret |= STPMIC1_LDO_VOUT(STPMIC1_LDO3_DDR_SEL);
> -
> -		ret = pmic_reg_write(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3),
> -				     ret);
> -		if (ret < 0)
> -			return ret;
> -
> -		/* VDD_DDR = Set BUCK2 to 1.35V */
> -		ret = pmic_clrsetbits(dev,
> -				      STPMIC1_BUCKX_MAIN_CR(STPMIC1_BUCK2),
> -				      STPMIC1_BUCK_VOUT_MASK,
> -				      STPMIC1_BUCK2_1350000V);
> -		if (ret < 0)
> -			return ret;
> -
> -		/* Enable VDD_DDR = BUCK2 */
> -		ret = pmic_clrsetbits(dev,
> -				      STPMIC1_BUCKX_MAIN_CR(STPMIC1_BUCK2),
> -				      STPMIC1_BUCK_ENA, STPMIC1_BUCK_ENA);
> -		if (ret < 0)
> -			return ret;
> -
> -		mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
> -
> -		/* Enable VREF */
> -		ret = pmic_clrsetbits(dev, STPMIC1_REFDDR_MAIN_CR,
> -				      STPMIC1_VREF_ENA, STPMIC1_VREF_ENA);
> -		if (ret < 0)
> -			return ret;
> -
> -		mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
> -
> -		/* Enable VTT = LDO3 */
> -		ret = pmic_clrsetbits(dev,
> -				      STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3),
> -				      STPMIC1_LDO_ENA, STPMIC1_LDO_ENA);
> -		if (ret < 0)
> -			return ret;
> -
> -		mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
> -
> -		break;
> -
> -	case STM32MP_LPDDR2_16:
> -	case STM32MP_LPDDR2_32:
> -	case STM32MP_LPDDR3_16:
> -	case STM32MP_LPDDR3_32:
> -		/*
> -		 * configure VDD_DDR1 = LDO3
> -		 * Set LDO3 to 1.8V
> -		 * + bypass mode if BUCK3 = 1.8V
> -		 * + normal mode if BUCK3 != 1.8V
> -		 */
> -		ret = pmic_reg_read(dev,
> -				    STPMIC1_BUCKX_MAIN_CR(STPMIC1_BUCK3));
> -		if (ret < 0)
> -			return ret;
> -
> -		if ((ret & STPMIC1_BUCK3_1800000V) == STPMIC1_BUCK3_1800000V)
> -			buck3_at_1800000v = true;
> -
> -		ret = pmic_reg_read(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3));
> -		if (ret < 0)
> -			return ret;
> -
> -		ret &= ~STPMIC1_LDO3_MODE;
> -		ret &= ~STPMIC1_LDO12356_VOUT_MASK;
> -		ret |= STPMIC1_LDO3_1800000;
> -		if (buck3_at_1800000v)
> -			ret |= STPMIC1_LDO3_MODE;
> -
> -		ret = pmic_reg_write(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3),
> -				     ret);
> -		if (ret < 0)
> -			return ret;
> -
> -		/* VDD_DDR2 : Set BUCK2 to 1.2V (16bits) or 1.25V (32 bits)*/
> -		switch (ddr_type) {
> -		case STM32MP_LPDDR2_32:
> -		case STM32MP_LPDDR3_32:
> -			buck2 = STPMIC1_BUCK2_1250000V;
> -			break;
> -		default:
> -		case STM32MP_LPDDR2_16:
> -		case STM32MP_LPDDR3_16:
> -			buck2 = STPMIC1_BUCK2_1200000V;
> -			break;
> -		}
> -
> -		ret = pmic_clrsetbits(dev,
> -				      STPMIC1_BUCKX_MAIN_CR(STPMIC1_BUCK2),
> -				      STPMIC1_BUCK_VOUT_MASK,
> -				      buck2);
> -		if (ret < 0)
> -			return ret;
> -
> -		/* Enable VDD_DDR1 = LDO3 */
> -		ret = pmic_clrsetbits(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3),
> -				      STPMIC1_LDO_ENA, STPMIC1_LDO_ENA);
> -		if (ret < 0)
> -			return ret;
> -
> -		mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
> -
> -		/* Enable VDD_DDR2 =BUCK2 */
> -		ret = pmic_clrsetbits(dev,
> -				      STPMIC1_BUCKX_MAIN_CR(STPMIC1_BUCK2),
> -				      STPMIC1_BUCK_ENA, STPMIC1_BUCK_ENA);
> -		if (ret < 0)
> -			return ret;
> -
> -		mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
> -
> -		/* Enable VREF */
> -		ret = pmic_clrsetbits(dev, STPMIC1_REFDDR_MAIN_CR,
> -				      STPMIC1_VREF_ENA, STPMIC1_VREF_ENA);
> -		if (ret < 0)
> -			return ret;
> -
> -		mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
> -
> -		break;
> -
> -	default:
> -		break;
> -	};
> -
> -	return 0;
> -}
> -#endif


Reviewed-by: Patrice Chotard <patrice.chotard at st.com>

Thanks

Patrice
diff mbox series

Patch

diff --git a/board/dhelectronics/dh_stm32mp1/Makefile b/board/dhelectronics/dh_stm32mp1/Makefile
index b42c4e4c04..04586c0a28 100644
--- a/board/dhelectronics/dh_stm32mp1/Makefile
+++ b/board/dhelectronics/dh_stm32mp1/Makefile
@@ -7,4 +7,4 @@  ifdef CONFIG_SPL_BUILD
 obj-y += ../../st/stm32mp1/spl.o
 endif
 
-obj-y += ../../st/stm32mp1/board.o board.o
+obj-y += ../../st/common/stpmic1.o board.o
diff --git a/board/st/common/Makefile b/board/st/common/Makefile
index 8553606b90..78bc0307f7 100644
--- a/board/st/common/Makefile
+++ b/board/st/common/Makefile
@@ -4,3 +4,4 @@ 
 #
 
 obj-$(CONFIG_CMD_STBOARD) += cmd_stboard.o
+obj-$(CONFIG_PMIC_STPMIC1) += stpmic1.o
diff --git a/board/st/common/stpmic1.c b/board/st/common/stpmic1.c
new file mode 100644
index 0000000000..ca10a2246b
--- /dev/null
+++ b/board/st/common/stpmic1.c
@@ -0,0 +1,162 @@ 
+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+/*
+ * Copyright (C) 2020, STMicroelectronics - All Rights Reserved
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <asm/arch/ddr.h>
+#include <power/pmic.h>
+#include <power/stpmic1.h>
+
+int board_ddr_power_init(enum ddr_type ddr_type)
+{
+	struct udevice *dev;
+	bool buck3_at_1800000v = false;
+	int ret;
+	u32 buck2;
+
+	ret = uclass_get_device_by_driver(UCLASS_PMIC,
+					  DM_GET_DRIVER(pmic_stpmic1), &dev);
+	if (ret)
+		/* No PMIC on board */
+		return 0;
+
+	switch (ddr_type) {
+	case STM32MP_DDR3:
+		/* VTT = Set LDO3 to sync mode */
+		ret = pmic_reg_read(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3));
+		if (ret < 0)
+			return ret;
+
+		ret &= ~STPMIC1_LDO3_MODE;
+		ret &= ~STPMIC1_LDO12356_VOUT_MASK;
+		ret |= STPMIC1_LDO_VOUT(STPMIC1_LDO3_DDR_SEL);
+
+		ret = pmic_reg_write(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3),
+				     ret);
+		if (ret < 0)
+			return ret;
+
+		/* VDD_DDR = Set BUCK2 to 1.35V */
+		ret = pmic_clrsetbits(dev,
+				      STPMIC1_BUCKX_MAIN_CR(STPMIC1_BUCK2),
+				      STPMIC1_BUCK_VOUT_MASK,
+				      STPMIC1_BUCK2_1350000V);
+		if (ret < 0)
+			return ret;
+
+		/* Enable VDD_DDR = BUCK2 */
+		ret = pmic_clrsetbits(dev,
+				      STPMIC1_BUCKX_MAIN_CR(STPMIC1_BUCK2),
+				      STPMIC1_BUCK_ENA, STPMIC1_BUCK_ENA);
+		if (ret < 0)
+			return ret;
+
+		mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
+
+		/* Enable VREF */
+		ret = pmic_clrsetbits(dev, STPMIC1_REFDDR_MAIN_CR,
+				      STPMIC1_VREF_ENA, STPMIC1_VREF_ENA);
+		if (ret < 0)
+			return ret;
+
+		mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
+
+		/* Enable VTT = LDO3 */
+		ret = pmic_clrsetbits(dev,
+				      STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3),
+				      STPMIC1_LDO_ENA, STPMIC1_LDO_ENA);
+		if (ret < 0)
+			return ret;
+
+		mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
+
+		break;
+
+	case STM32MP_LPDDR2_16:
+	case STM32MP_LPDDR2_32:
+	case STM32MP_LPDDR3_16:
+	case STM32MP_LPDDR3_32:
+		/*
+		 * configure VDD_DDR1 = LDO3
+		 * Set LDO3 to 1.8V
+		 * + bypass mode if BUCK3 = 1.8V
+		 * + normal mode if BUCK3 != 1.8V
+		 */
+		ret = pmic_reg_read(dev,
+				    STPMIC1_BUCKX_MAIN_CR(STPMIC1_BUCK3));
+		if (ret < 0)
+			return ret;
+
+		if ((ret & STPMIC1_BUCK3_1800000V) == STPMIC1_BUCK3_1800000V)
+			buck3_at_1800000v = true;
+
+		ret = pmic_reg_read(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3));
+		if (ret < 0)
+			return ret;
+
+		ret &= ~STPMIC1_LDO3_MODE;
+		ret &= ~STPMIC1_LDO12356_VOUT_MASK;
+		ret |= STPMIC1_LDO3_1800000;
+		if (buck3_at_1800000v)
+			ret |= STPMIC1_LDO3_MODE;
+
+		ret = pmic_reg_write(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3),
+				     ret);
+		if (ret < 0)
+			return ret;
+
+		/* VDD_DDR2 : Set BUCK2 to 1.2V (16bits) or 1.25V (32 bits)*/
+		switch (ddr_type) {
+		case STM32MP_LPDDR2_32:
+		case STM32MP_LPDDR3_32:
+			buck2 = STPMIC1_BUCK2_1250000V;
+			break;
+		default:
+		case STM32MP_LPDDR2_16:
+		case STM32MP_LPDDR3_16:
+			buck2 = STPMIC1_BUCK2_1200000V;
+			break;
+		}
+
+		ret = pmic_clrsetbits(dev,
+				      STPMIC1_BUCKX_MAIN_CR(STPMIC1_BUCK2),
+				      STPMIC1_BUCK_VOUT_MASK,
+				      buck2);
+		if (ret < 0)
+			return ret;
+
+		/* Enable VDD_DDR1 = LDO3 */
+		ret = pmic_clrsetbits(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3),
+				      STPMIC1_LDO_ENA, STPMIC1_LDO_ENA);
+		if (ret < 0)
+			return ret;
+
+		mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
+
+		/* Enable VDD_DDR2 =BUCK2 */
+		ret = pmic_clrsetbits(dev,
+				      STPMIC1_BUCKX_MAIN_CR(STPMIC1_BUCK2),
+				      STPMIC1_BUCK_ENA, STPMIC1_BUCK_ENA);
+		if (ret < 0)
+			return ret;
+
+		mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
+
+		/* Enable VREF */
+		ret = pmic_clrsetbits(dev, STPMIC1_REFDDR_MAIN_CR,
+				      STPMIC1_VREF_ENA, STPMIC1_VREF_ENA);
+		if (ret < 0)
+			return ret;
+
+		mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
+
+		break;
+
+	default:
+		break;
+	};
+
+	return 0;
+}
diff --git a/board/st/stm32mp1/board.c b/board/st/stm32mp1/board.c
index 4e35d36c76..1887941e57 100644
--- a/board/st/stm32mp1/board.c
+++ b/board/st/stm32mp1/board.c
@@ -4,11 +4,7 @@ 
  */
 
 #include <common.h>
-#include <dm.h>
 #include <asm/io.h>
-#include <asm/arch/ddr.h>
-#include <power/pmic.h>
-#include <power/stpmic1.h>
 
 #ifdef CONFIG_DEBUG_UART_BOARD_INIT
 void board_debug_uart_init(void)
@@ -36,157 +32,3 @@  void board_debug_uart_init(void)
 #endif
 }
 #endif
-
-#ifdef CONFIG_PMIC_STPMIC1
-int board_ddr_power_init(enum ddr_type ddr_type)
-{
-	struct udevice *dev;
-	bool buck3_at_1800000v = false;
-	int ret;
-	u32 buck2;
-
-	ret = uclass_get_device_by_driver(UCLASS_PMIC,
-					  DM_GET_DRIVER(pmic_stpmic1), &dev);
-	if (ret)
-		/* No PMIC on board */
-		return 0;
-
-	switch (ddr_type) {
-	case STM32MP_DDR3:
-		/* VTT = Set LDO3 to sync mode */
-		ret = pmic_reg_read(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3));
-		if (ret < 0)
-			return ret;
-
-		ret &= ~STPMIC1_LDO3_MODE;
-		ret &= ~STPMIC1_LDO12356_VOUT_MASK;
-		ret |= STPMIC1_LDO_VOUT(STPMIC1_LDO3_DDR_SEL);
-
-		ret = pmic_reg_write(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3),
-				     ret);
-		if (ret < 0)
-			return ret;
-
-		/* VDD_DDR = Set BUCK2 to 1.35V */
-		ret = pmic_clrsetbits(dev,
-				      STPMIC1_BUCKX_MAIN_CR(STPMIC1_BUCK2),
-				      STPMIC1_BUCK_VOUT_MASK,
-				      STPMIC1_BUCK2_1350000V);
-		if (ret < 0)
-			return ret;
-
-		/* Enable VDD_DDR = BUCK2 */
-		ret = pmic_clrsetbits(dev,
-				      STPMIC1_BUCKX_MAIN_CR(STPMIC1_BUCK2),
-				      STPMIC1_BUCK_ENA, STPMIC1_BUCK_ENA);
-		if (ret < 0)
-			return ret;
-
-		mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
-
-		/* Enable VREF */
-		ret = pmic_clrsetbits(dev, STPMIC1_REFDDR_MAIN_CR,
-				      STPMIC1_VREF_ENA, STPMIC1_VREF_ENA);
-		if (ret < 0)
-			return ret;
-
-		mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
-
-		/* Enable VTT = LDO3 */
-		ret = pmic_clrsetbits(dev,
-				      STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3),
-				      STPMIC1_LDO_ENA, STPMIC1_LDO_ENA);
-		if (ret < 0)
-			return ret;
-
-		mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
-
-		break;
-
-	case STM32MP_LPDDR2_16:
-	case STM32MP_LPDDR2_32:
-	case STM32MP_LPDDR3_16:
-	case STM32MP_LPDDR3_32:
-		/*
-		 * configure VDD_DDR1 = LDO3
-		 * Set LDO3 to 1.8V
-		 * + bypass mode if BUCK3 = 1.8V
-		 * + normal mode if BUCK3 != 1.8V
-		 */
-		ret = pmic_reg_read(dev,
-				    STPMIC1_BUCKX_MAIN_CR(STPMIC1_BUCK3));
-		if (ret < 0)
-			return ret;
-
-		if ((ret & STPMIC1_BUCK3_1800000V) == STPMIC1_BUCK3_1800000V)
-			buck3_at_1800000v = true;
-
-		ret = pmic_reg_read(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3));
-		if (ret < 0)
-			return ret;
-
-		ret &= ~STPMIC1_LDO3_MODE;
-		ret &= ~STPMIC1_LDO12356_VOUT_MASK;
-		ret |= STPMIC1_LDO3_1800000;
-		if (buck3_at_1800000v)
-			ret |= STPMIC1_LDO3_MODE;
-
-		ret = pmic_reg_write(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3),
-				     ret);
-		if (ret < 0)
-			return ret;
-
-		/* VDD_DDR2 : Set BUCK2 to 1.2V (16bits) or 1.25V (32 bits)*/
-		switch (ddr_type) {
-		case STM32MP_LPDDR2_32:
-		case STM32MP_LPDDR3_32:
-			buck2 = STPMIC1_BUCK2_1250000V;
-			break;
-		default:
-		case STM32MP_LPDDR2_16:
-		case STM32MP_LPDDR3_16:
-			buck2 = STPMIC1_BUCK2_1200000V;
-			break;
-		}
-
-		ret = pmic_clrsetbits(dev,
-				      STPMIC1_BUCKX_MAIN_CR(STPMIC1_BUCK2),
-				      STPMIC1_BUCK_VOUT_MASK,
-				      buck2);
-		if (ret < 0)
-			return ret;
-
-		/* Enable VDD_DDR1 = LDO3 */
-		ret = pmic_clrsetbits(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3),
-				      STPMIC1_LDO_ENA, STPMIC1_LDO_ENA);
-		if (ret < 0)
-			return ret;
-
-		mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
-
-		/* Enable VDD_DDR2 =BUCK2 */
-		ret = pmic_clrsetbits(dev,
-				      STPMIC1_BUCKX_MAIN_CR(STPMIC1_BUCK2),
-				      STPMIC1_BUCK_ENA, STPMIC1_BUCK_ENA);
-		if (ret < 0)
-			return ret;
-
-		mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
-
-		/* Enable VREF */
-		ret = pmic_clrsetbits(dev, STPMIC1_REFDDR_MAIN_CR,
-				      STPMIC1_VREF_ENA, STPMIC1_VREF_ENA);
-		if (ret < 0)
-			return ret;
-
-		mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
-
-		break;
-
-	default:
-		break;
-	};
-
-	return 0;
-}
-#endif