| Message ID | 20200421171123.2.Id3620aec4deb419f1c1a5876b865556e86d3aba1@changeid |
|---|---|
| State | Superseded |
| Headers | show |
| Series | stm32mp1: use OPP information for PLL1 settings in SPL | expand |
Hi Patrick On 4/21/20 5:11 PM, Patrick Delaunay wrote: > This commit adds cpufreq support on stm32mp15x SOC. STM32 cpufreq uses > operating points V2 bindings (no legacy). Nvmem cells have to be used to > know the chip version and then which OPPs are available. Note that STM32 > cpufreq driver is mainly based on "cpufreq-dt" driver. > > Signed-off-by: Patrick Delaunay <patrick.delaunay at st.com> > --- > > arch/arm/dts/stm32mp151.dtsi | 21 +++++++++++++++++++++ > arch/arm/dts/stm32mp157c-ed1.dts | 8 ++++++++ > arch/arm/dts/stm32mp15xx-dkx.dtsi | 8 ++++++++ > 3 files changed, 37 insertions(+) > > diff --git a/arch/arm/dts/stm32mp151.dtsi b/arch/arm/dts/stm32mp151.dtsi > index f185639a46..1d465c3064 100644 > --- a/arch/arm/dts/stm32mp151.dtsi > +++ b/arch/arm/dts/stm32mp151.dtsi > @@ -19,6 +19,24 @@ > compatible = "arm,cortex-a7"; > device_type = "cpu"; > reg = <0>; > + operating-points-v2 = <&cpu0_opp_table>; > + nvmem-cells = <&part_number_otp>; > + nvmem-cell-names = "part_number"; > + }; > + }; > + > + cpu0_opp_table: cpu0-opp-table { > + compatible = "operating-points-v2"; > + opp-shared; > + opp-650000000 { > + opp-hz = /bits/ 64 <650000000>; > + opp-microvolt = <1200000>; > + opp-supported-hw = <0x1>; > + }; > + opp-800000000 { > + opp-hz = /bits/ 64 <800000000>; > + opp-microvolt = <1350000>; > + opp-supported-hw = <0x2>; > }; > }; > > @@ -1512,6 +1530,9 @@ > reg = <0x5c005000 0x400>; > #address-cells = <1>; > #size-cells = <1>; > + part_number_otp: part_number_otp at 4 { > + reg = <0x4 0x1>; > + }; > ts_cal1: calib at 5c { > reg = <0x5c 0x2>; > }; > diff --git a/arch/arm/dts/stm32mp157c-ed1.dts b/arch/arm/dts/stm32mp157c-ed1.dts > index 54af7c97b3..7215eb4768 100644 > --- a/arch/arm/dts/stm32mp157c-ed1.dts > +++ b/arch/arm/dts/stm32mp157c-ed1.dts > @@ -107,6 +107,14 @@ > }; > }; > > +&cpu0{ > + cpu-supply = <&vddcore>; > +}; > + > +&cpu1{ > + cpu-supply = <&vddcore>; > +}; > + > &dac { > pinctrl-names = "default"; > pinctrl-0 = <&dac_ch1_pins_a &dac_ch2_pins_a>; > diff --git a/arch/arm/dts/stm32mp15xx-dkx.dtsi b/arch/arm/dts/stm32mp15xx-dkx.dtsi > index 42d3f0cb2d..861280afe8 100644 > --- a/arch/arm/dts/stm32mp15xx-dkx.dtsi > +++ b/arch/arm/dts/stm32mp15xx-dkx.dtsi > @@ -116,6 +116,14 @@ > status = "okay"; > }; > > +&cpu0{ > + cpu-supply = <&vddcore>; > +}; > + > +&cpu1{ > + cpu-supply = <&vddcore>; > +}; > + > ðernet0 { > status = "okay"; > pinctrl-0 = <ðernet0_rgmii_pins_a>; Reviewed-by: Patrice Chotard <patrice.chotard at st.com> Thanks Patrice
diff --git a/arch/arm/dts/stm32mp151.dtsi b/arch/arm/dts/stm32mp151.dtsi index f185639a46..1d465c3064 100644 --- a/arch/arm/dts/stm32mp151.dtsi +++ b/arch/arm/dts/stm32mp151.dtsi @@ -19,6 +19,24 @@ compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <0>; + operating-points-v2 = <&cpu0_opp_table>; + nvmem-cells = <&part_number_otp>; + nvmem-cell-names = "part_number"; + }; + }; + + cpu0_opp_table: cpu0-opp-table { + compatible = "operating-points-v2"; + opp-shared; + opp-650000000 { + opp-hz = /bits/ 64 <650000000>; + opp-microvolt = <1200000>; + opp-supported-hw = <0x1>; + }; + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <1350000>; + opp-supported-hw = <0x2>; }; }; @@ -1512,6 +1530,9 @@ reg = <0x5c005000 0x400>; #address-cells = <1>; #size-cells = <1>; + part_number_otp: part_number_otp at 4 { + reg = <0x4 0x1>; + }; ts_cal1: calib at 5c { reg = <0x5c 0x2>; }; diff --git a/arch/arm/dts/stm32mp157c-ed1.dts b/arch/arm/dts/stm32mp157c-ed1.dts index 54af7c97b3..7215eb4768 100644 --- a/arch/arm/dts/stm32mp157c-ed1.dts +++ b/arch/arm/dts/stm32mp157c-ed1.dts @@ -107,6 +107,14 @@ }; }; +&cpu0{ + cpu-supply = <&vddcore>; +}; + +&cpu1{ + cpu-supply = <&vddcore>; +}; + &dac { pinctrl-names = "default"; pinctrl-0 = <&dac_ch1_pins_a &dac_ch2_pins_a>; diff --git a/arch/arm/dts/stm32mp15xx-dkx.dtsi b/arch/arm/dts/stm32mp15xx-dkx.dtsi index 42d3f0cb2d..861280afe8 100644 --- a/arch/arm/dts/stm32mp15xx-dkx.dtsi +++ b/arch/arm/dts/stm32mp15xx-dkx.dtsi @@ -116,6 +116,14 @@ status = "okay"; }; +&cpu0{ + cpu-supply = <&vddcore>; +}; + +&cpu1{ + cpu-supply = <&vddcore>; +}; + ðernet0 { status = "okay"; pinctrl-0 = <ðernet0_rgmii_pins_a>;
This commit adds cpufreq support on stm32mp15x SOC. STM32 cpufreq uses operating points V2 bindings (no legacy). Nvmem cells have to be used to know the chip version and then which OPPs are available. Note that STM32 cpufreq driver is mainly based on "cpufreq-dt" driver. Signed-off-by: Patrick Delaunay <patrick.delaunay at st.com> --- arch/arm/dts/stm32mp151.dtsi | 21 +++++++++++++++++++++ arch/arm/dts/stm32mp157c-ed1.dts | 8 ++++++++ arch/arm/dts/stm32mp15xx-dkx.dtsi | 8 ++++++++ 3 files changed, 37 insertions(+)