| Message ID | 20200430070412.12499-9-jagan@amarulasolutions.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | rockchip: Add PCIe host support | expand |
On Thu, Apr 30, 2020 at 12:34:12PM +0530, Jagan Teki wrote: > Due to some on board limitation rock960 PCIe > works only with 1.8V IO domain. > > So, this patch enables grf io_sel explicitly > to make PCIe/M.2 to work. > > Cc: Tom Cubie <tom at radxa.com> > Cc: Manivannan Sadhasivam <manivannan.sadhasivam at linaro.org> > Signed-off-by: Jagan Teki <jagan at amarulasolutions.com> > --- > Changes for v2: > - none > > board/vamrs/rock960_rk3399/rock960-rk3399.c | 20 ++++++++++++++++++++ > configs/rock960-rk3399_defconfig | 5 +++++ > 2 files changed, 25 insertions(+) > > diff --git a/board/vamrs/rock960_rk3399/rock960-rk3399.c b/board/vamrs/rock960_rk3399/rock960-rk3399.c > index 68a127b9ac..98d62e89ca 100644 > --- a/board/vamrs/rock960_rk3399/rock960-rk3399.c > +++ b/board/vamrs/rock960_rk3399/rock960-rk3399.c > @@ -2,3 +2,23 @@ > /* > * Copyright (C) 2018 Manivannan Sadhasivam <manivannan.sadhasivam at linaro.org> > */ > + > +#include <common.h> > +#include <syscon.h> > +#include <asm/io.h> > +#include <asm/arch-rockchip/clock.h> > +#include <asm/arch-rockchip/grf_rk3399.h> > +#include <asm/arch-rockchip/hardware.h> > + > +#ifdef CONFIG_MISC_INIT_R > +int misc_init_r(void) > +{ > + struct rk3399_grf_regs *grf = > + syscon_get_first_range(ROCKCHIP_SYSCON_GRF); > + > + /* BT565 is in 1.8v domain */ >From where this BT565 comes in? Anyway, I don't have the PCI-E device with me to test this change but it looks good to me. Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam at linaro.org> PS: Added Peter to CC incase he is interested. Thanks, Mani > + rk_setreg(&grf->io_vsel, BIT(0)); > + > + return 0; > +} > +#endif > diff --git a/configs/rock960-rk3399_defconfig b/configs/rock960-rk3399_defconfig > index c4e954731a..cb1ec3c26b 100644 > --- a/configs/rock960-rk3399_defconfig > +++ b/configs/rock960-rk3399_defconfig > @@ -9,6 +9,7 @@ CONFIG_DEBUG_UART_BASE=0xFF1A0000 > CONFIG_DEBUG_UART_CLOCK=24000000 > CONFIG_DEBUG_UART=y > CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock960.dtb" > +CONFIG_MISC_INIT_R=y > CONFIG_DISPLAY_BOARDINFO_LATE=y > # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set > CONFIG_SPL_STACK_R=y > @@ -19,6 +20,7 @@ CONFIG_CMD_BOOTZ=y > CONFIG_CMD_GPT=y > CONFIG_CMD_MMC=y > CONFIG_CMD_USB=y > +CONFIG_CMD_PCI=y > # CONFIG_CMD_SETEXPR is not set > CONFIG_CMD_TIME=y > CONFIG_CMD_PMIC=y > @@ -36,10 +38,13 @@ CONFIG_MMC_SDHCI=y > CONFIG_MMC_SDHCI_SDMA=y > CONFIG_MMC_SDHCI_ROCKCHIP=y > CONFIG_DM_ETH=y > +CONFIG_NVME=y > +CONFIG_PCI=y > CONFIG_PMIC_RK8XX=y > CONFIG_REGULATOR_PWM=y > CONFIG_REGULATOR_RK8XX=y > CONFIG_PWM_ROCKCHIP=y > +CONFIG_DM_RESET=y > CONFIG_BAUDRATE=1500000 > CONFIG_DEBUG_UART_SHIFT=2 > CONFIG_SYSRESET=y > -- > 2.17.1 >
On Sun, May 3, 2020 at 7:09 PM Manivannan Sadhasivam <manivannan.sadhasivam at linaro.org> wrote: > > On Thu, Apr 30, 2020 at 12:34:12PM +0530, Jagan Teki wrote: > > Due to some on board limitation rock960 PCIe > > works only with 1.8V IO domain. > > > > So, this patch enables grf io_sel explicitly > > to make PCIe/M.2 to work. > > > > Cc: Tom Cubie <tom at radxa.com> > > Cc: Manivannan Sadhasivam <manivannan.sadhasivam at linaro.org> > > Signed-off-by: Jagan Teki <jagan at amarulasolutions.com> > > --- > > Changes for v2: > > - none > > > > board/vamrs/rock960_rk3399/rock960-rk3399.c | 20 ++++++++++++++++++++ > > configs/rock960-rk3399_defconfig | 5 +++++ > > 2 files changed, 25 insertions(+) > > > > diff --git a/board/vamrs/rock960_rk3399/rock960-rk3399.c b/board/vamrs/rock960_rk3399/rock960-rk3399.c > > index 68a127b9ac..98d62e89ca 100644 > > --- a/board/vamrs/rock960_rk3399/rock960-rk3399.c > > +++ b/board/vamrs/rock960_rk3399/rock960-rk3399.c > > @@ -2,3 +2,23 @@ > > /* > > * Copyright (C) 2018 Manivannan Sadhasivam <manivannan.sadhasivam at linaro.org> > > */ > > + > > +#include <common.h> > > +#include <syscon.h> > > +#include <asm/io.h> > > +#include <asm/arch-rockchip/clock.h> > > +#include <asm/arch-rockchip/grf_rk3399.h> > > +#include <asm/arch-rockchip/hardware.h> > > + > > +#ifdef CONFIG_MISC_INIT_R > > +int misc_init_r(void) > > +{ > > + struct rk3399_grf_regs *grf = > > + syscon_get_first_range(ROCKCHIP_SYSCON_GRF); > > + > > + /* BT565 is in 1.8v domain */ > > From where this BT565 comes in? If my understanding was correct, some SSD's to work on this board do require this explicit domain voltage change. Usually it requires GPIO enablement followed by grf voltage domain update [1] but in my case it worked w/o gpio. Maybe I will update this details in the commit message and also in the code. [1] https://github.com/radxa/u-boot/blob/stable-4.4-rockpi4/board/rockchip/evb_rk3399/evb-rk3399.c#L194 Jagan.
diff --git a/board/vamrs/rock960_rk3399/rock960-rk3399.c b/board/vamrs/rock960_rk3399/rock960-rk3399.c index 68a127b9ac..98d62e89ca 100644 --- a/board/vamrs/rock960_rk3399/rock960-rk3399.c +++ b/board/vamrs/rock960_rk3399/rock960-rk3399.c @@ -2,3 +2,23 @@ /* * Copyright (C) 2018 Manivannan Sadhasivam <manivannan.sadhasivam at linaro.org> */ + +#include <common.h> +#include <syscon.h> +#include <asm/io.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/grf_rk3399.h> +#include <asm/arch-rockchip/hardware.h> + +#ifdef CONFIG_MISC_INIT_R +int misc_init_r(void) +{ + struct rk3399_grf_regs *grf = + syscon_get_first_range(ROCKCHIP_SYSCON_GRF); + + /* BT565 is in 1.8v domain */ + rk_setreg(&grf->io_vsel, BIT(0)); + + return 0; +} +#endif diff --git a/configs/rock960-rk3399_defconfig b/configs/rock960-rk3399_defconfig index c4e954731a..cb1ec3c26b 100644 --- a/configs/rock960-rk3399_defconfig +++ b/configs/rock960-rk3399_defconfig @@ -9,6 +9,7 @@ CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock960.dtb" +CONFIG_MISC_INIT_R=y CONFIG_DISPLAY_BOARDINFO_LATE=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_STACK_R=y @@ -19,6 +20,7 @@ CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y +CONFIG_CMD_PCI=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y CONFIG_CMD_PMIC=y @@ -36,10 +38,13 @@ CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y CONFIG_DM_ETH=y +CONFIG_NVME=y +CONFIG_PCI=y CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y +CONFIG_DM_RESET=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYSRESET=y
Due to some on board limitation rock960 PCIe works only with 1.8V IO domain. So, this patch enables grf io_sel explicitly to make PCIe/M.2 to work. Cc: Tom Cubie <tom at radxa.com> Cc: Manivannan Sadhasivam <manivannan.sadhasivam at linaro.org> Signed-off-by: Jagan Teki <jagan at amarulasolutions.com> --- Changes for v2: - none board/vamrs/rock960_rk3399/rock960-rk3399.c | 20 ++++++++++++++++++++ configs/rock960-rk3399_defconfig | 5 +++++ 2 files changed, 25 insertions(+)