[RFC,5/7] arm64: dts: rk3399: Move pcie_phy into root port

Message ID 20200430214529.18887-6-jagan@amarulasolutions.com
State New
Headers show
Series
  • rockchip: Add PHY drivers
Related show

Commit Message

Jagan Teki April 30, 2020, 9:45 p.m.
Yes, This is changing the actual device tree pcie_phy
structure but the problem with the current Generic PHY
subsystem is unable to find PHY if the PHY node is not
part of the root structure and also PHY parent is
non-PHY type.

This will be reverted once we support the PHY subsystem
to get the PHY whose parent has non-PHY type or any other
relevant solution.? ?

Signed-off-by: Jagan Teki <jagan at amarulasolutions.com>
---
 arch/arm/dts/rk3399.dtsi | 20 ++++++++++----------
 1 file changed, 10 insertions(+), 10 deletions(-)

Patch

diff --git a/arch/arm/dts/rk3399.dtsi b/arch/arm/dts/rk3399.dtsi
index 6c77f25f23..dea76032bf 100644
--- a/arch/arm/dts/rk3399.dtsi
+++ b/arch/arm/dts/rk3399.dtsi
@@ -1395,17 +1395,17 @@ 
 			#phy-cells = <0>;
 			status = "disabled";
 		};
+	};
 
-		pcie_phy: pcie-phy {
-			compatible = "rockchip,rk3399-pcie-phy";
-			clocks = <&cru SCLK_PCIEPHY_REF>;
-			clock-names = "refclk";
-			#phy-cells = <1>;
-			resets = <&cru SRST_PCIEPHY>;
-			drive-impedance-ohm = <50>;
-			reset-names = "phy";
-			status = "disabled";
-		};
+	pcie_phy: pcie-phy {
+		compatible = "rockchip,rk3399-pcie-phy";
+		clocks = <&cru SCLK_PCIEPHY_REF>;
+		clock-names = "refclk";
+		#phy-cells = <1>;
+		resets = <&cru SRST_PCIEPHY>;
+		drive-impedance-ohm = <50>;
+		reset-names = "phy";
+		status = "disabled";
 	};
 
 	u2phy0: usb2-phy at e450 {