@@ -15,4 +15,21 @@ config TARGET_CLEARFOG_BASE
detection via additional EEPROM hardware. This option enables selecting
the Base variant for older hardware revisions.
+config CLEARFOG_CON3_SATA
+ bool "Use CON3 slot in SATA mode"
+ help
+ Use the CON3 port with SATA protocol instead of the default PCIe.
+ The ClearFog port allows usage of either mSATA or miniPCIe
+ modules, but the desired protocol must be configured at build
+ time since it affects the SerDes topology layout.
+
+config CLEARFOG_CON2_SATA
+ bool "Use CON2 slot in SATA mode"
+ depends on !TARGET_CLEARFOG_BASE
+ help
+ Use the CON2 port with SATA protocol instead of the default PCIe.
+ The ClearFog port allows usage of either mSATA or miniPCIe
+ modules, but the desired protocol must be configured at build
+ time since it affects the SerDes topology layout.
+
endmenu
@@ -42,10 +42,16 @@ static void read_tlv_data(void);
static struct serdes_map board_serdes_map[] = {
{SATA0, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 0},
{SGMII1, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0},
+#if defined (CONFIG_CLEARFOG_CON3_SATA)
+ {SATA1, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 0},
+#else
{PEX1, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
+#endif
{USB3_HOST1, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
#if defined (CONFIG_TARGET_CLEARFOG_BASE)
{USB3_HOST0, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
+#elif defined(CONFIG_CLEARFOG_CON2_SATA)
+ {SATA2, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 0},
#else
{PEX2, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
#endif
The mPCIe slots on ClearFog Pro and ClearFog Base may be alternately configured for SATA usage. Signed-off-by: Joel Johnson <mrjoel at lixil.net> --- v2 changes: - fixed help indentation --- board/solidrun/clearfog/Kconfig | 17 +++++++++++++++++ board/solidrun/clearfog/clearfog.c | 6 ++++++ 2 files changed, 23 insertions(+)