From patchwork Mon Jan 27 05:06:28 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 240231 List-Id: U-Boot discussion From: sjg at chromium.org (Simon Glass) Date: Sun, 26 Jan 2020 22:06:28 -0700 Subject: [PATCH 081/108] x86: apl: Update iomap for ACPI In-Reply-To: <20200127050655.170614-1-sjg@chromium.org> References: <20200127050655.170614-1-sjg@chromium.org> Message-ID: <20200126220508.81.I917883a8fac7a88a31608348bfafd057fd49b801@changeid> Add some more definitions to the iomap. These will be used by ACPI-generation code as well as the device tree. Signed-off-by: Simon Glass --- arch/x86/include/asm/arch-apollolake/iomap.h | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/x86/include/asm/arch-apollolake/iomap.h b/arch/x86/include/asm/arch-apollolake/iomap.h index 4ce1017055..d12268c825 100644 --- a/arch/x86/include/asm/arch-apollolake/iomap.h +++ b/arch/x86/include/asm/arch-apollolake/iomap.h @@ -11,11 +11,28 @@ /* Put p2sb at 0xd0000000 in TPL */ #define IOMAP_P2SB_BAR 0xd0000000 +#define IOMAP_P2SB_SIZE 0x10000000 #define IOMAP_SPI_BASE 0xfe010000 #define IOMAP_ACPI_BASE 0x400 #define IOMAP_ACPI_SIZE 0x100 +#define ACPI_BASE_ADDRESS IOMAP_ACPI_BASE + +#define PMC_BAR0 0xfe042000 + +#define MCH_BASE_ADDRESS 0xfed10000 +#define MCH_SIZE 0x8000 +#ifdef __ACPI__ +#define HPET_BASE_ADDRESS 0xfed00000 + +#define PMC_BAR0 0xfe042000 + +#define SRAM_BASE_0 0xfe900000 +#define SRAM_SIZE_0 (8 * KiB) +#define SRAM_BASE_2 0xfe902000 +#define SRAM_SIZE_2 (4 * KiB) +#endif /* * Use UART2. To use UART1 you need to set '2' to '1', change device tree serial