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[v2,1/2] drivers: p2sb: replace Primary-to-Sideband Bus with Primary to Sideband Bridge

Message ID 20200701090642.232739-2-wolfgang.wallner@br-automation.com
State Superseded
Headers show
Series x86: p2sb: P2SB fixes | expand

Commit Message

Wolfgang Wallner July 1, 2020, 9:06 a.m. UTC 
In Intel's documentation the term P2SB stands for "Primary to Sideband
Bridge".

Signed-off-by: Wolfgang Wallner <wolfgang.wallner at br-automation.com>
---

(no changes since v1)

 drivers/misc/Kconfig | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)
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Patch

diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index 6bb5bc77e9..b6b8510e40 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -243,10 +243,10 @@  config NUVOTON_NCT6102D
 	  in the Nuvoton Super IO chips on X86 platforms.
 
 config P2SB
-	bool "Intel Primary-to-Sideband Bus"
+	bool "Intel Primary to Sideband Bridge"
 	depends on X86 || SANDBOX
 	help
-	  This enables support for the Intel Primary-to-Sideband bus,
+	  This enables support for the Intel Primary to Sideband Bridge,
 	  abbreviated to P2SB. The P2SB is used to access various peripherals
 	  such as eSPI, GPIO, through memory-mapped I/O in a large chunk of PCI
 	  space. The space is segmented into different channels and peripherals
@@ -259,7 +259,7 @@  config SPL_P2SB
 	bool "Intel Primary-to-Sideband Bus in SPL"
 	depends on SPL && (X86 || SANDBOX)
 	help
-	  The Primary-to-Sideband bus is used to access various peripherals
+	  The Primary to Sideband Bridge is used to access various peripherals
 	  through memory-mapped I/O in a large chunk of PCI space. The space is
 	  segmented into different channels and peripherals are accessed by
 	  device-specific means within those channels. Devices should be added
@@ -269,7 +269,7 @@  config TPL_P2SB
 	bool "Intel Primary-to-Sideband Bus in TPL"
 	depends on TPL && (X86 || SANDBOX)
 	help
-	  The Primary-to-Sideband bus is used to access various peripherals
+	  The Primary to Sideband Bridge is used to access various peripherals
 	  through memory-mapped I/O in a large chunk of PCI space. The space is
 	  segmented into different channels and peripherals are accessed by
 	  device-specific means within those channels. Devices should be added