diff mbox series

[v3,1/2] drivers: p2sb: replace Primary-to-Sideband Bus with Primary to Sideband Bridge

Message ID 20200701113724.255226-2-wolfgang.wallner@br-automation.com
State Accepted
Commit d872e7da7a7e5c7199fa59506e08524277621649
Headers show
Series x86: p2sb: P2SB fixes | expand

Commit Message

Wolfgang Wallner July 1, 2020, 11:37 a.m. UTC 
In Intel's documentation the term P2SB stands for "Primary to Sideband
Bridge".

Signed-off-by: Wolfgang Wallner <wolfgang.wallner at br-automation.com>
---

Changes in v3:
- Replaced the term in two more places

 drivers/misc/Kconfig | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

Comments

Simon Glass July 3, 2020, 3:50 a.m. UTC | #1 
On Wed, 1 Jul 2020 at 05:37, Wolfgang Wallner
<wolfgang.wallner at br-automation.com> wrote:
>
> In Intel's documentation the term P2SB stands for "Primary to Sideband
> Bridge".
>
> Signed-off-by: Wolfgang Wallner <wolfgang.wallner at br-automation.com>
> ---
>
> Changes in v3:
> - Replaced the term in two more places
>
>  drivers/misc/Kconfig | 12 ++++++------
>  1 file changed, 6 insertions(+), 6 deletions(-)

Reviewed-by: Simon Glass <sjg at chromium.org>
Bin Meng July 13, 2020, 2 a.m. UTC | #2 
On Wed, Jul 1, 2020 at 7:37 PM Wolfgang Wallner
<wolfgang.wallner at br-automation.com> wrote:
>
> In Intel's documentation the term P2SB stands for "Primary to Sideband
> Bridge".
>
> Signed-off-by: Wolfgang Wallner <wolfgang.wallner at br-automation.com>
> ---
>
> Changes in v3:
> - Replaced the term in two more places
>
>  drivers/misc/Kconfig | 12 ++++++------
>  1 file changed, 6 insertions(+), 6 deletions(-)
>

applied to u-boot-x86, thanks!
diff mbox series

Patch

diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index 6bb5bc77e9..b67e906a76 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -243,10 +243,10 @@  config NUVOTON_NCT6102D
 	  in the Nuvoton Super IO chips on X86 platforms.
 
 config P2SB
-	bool "Intel Primary-to-Sideband Bus"
+	bool "Intel Primary to Sideband Bridge"
 	depends on X86 || SANDBOX
 	help
-	  This enables support for the Intel Primary-to-Sideband bus,
+	  This enables support for the Intel Primary to Sideband Bridge,
 	  abbreviated to P2SB. The P2SB is used to access various peripherals
 	  such as eSPI, GPIO, through memory-mapped I/O in a large chunk of PCI
 	  space. The space is segmented into different channels and peripherals
@@ -256,20 +256,20 @@  config P2SB
 	  devices - see pcr_readl(), etc.
 
 config SPL_P2SB
-	bool "Intel Primary-to-Sideband Bus in SPL"
+	bool "Intel Primary to Sideband Bridge in SPL"
 	depends on SPL && (X86 || SANDBOX)
 	help
-	  The Primary-to-Sideband bus is used to access various peripherals
+	  The Primary to Sideband Bridge is used to access various peripherals
 	  through memory-mapped I/O in a large chunk of PCI space. The space is
 	  segmented into different channels and peripherals are accessed by
 	  device-specific means within those channels. Devices should be added
 	  in the device tree as subnodes of the p2sb.
 
 config TPL_P2SB
-	bool "Intel Primary-to-Sideband Bus in TPL"
+	bool "Intel Primary to Sideband Bridge in TPL"
 	depends on TPL && (X86 || SANDBOX)
 	help
-	  The Primary-to-Sideband bus is used to access various peripherals
+	  The Primary to Sideband Bridge is used to access various peripherals
 	  through memory-mapped I/O in a large chunk of PCI space. The space is
 	  segmented into different channels and peripherals are accessed by
 	  device-specific means within those channels. Devices should be added