From patchwork Mon Jul 6 02:21:46 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?Q2h1bmZlbmcgWXVuICjkupHmmKXls7Ap?= X-Patchwork-Id: 240749 List-Id: U-Boot discussion From: chunfeng.yun at mediatek.com (Chunfeng Yun) Date: Mon, 6 Jul 2020 10:21:46 +0800 Subject: [PATCH v2 2/6] dt-bindings: usb: mtu3: add bindings for MediaTek USB3 DRD In-Reply-To: <1594002110-25624-1-git-send-email-chunfeng.yun@mediatek.com> References: <1594002110-25624-1-git-send-email-chunfeng.yun@mediatek.com> Message-ID: <1594002110-25624-3-git-send-email-chunfeng.yun@mediatek.com> Add dt-binding for MediaTek USB3 DRD Driver Signed-off-by: Chunfeng Yun --- v2: no changes --- doc/device-tree-bindings/usb/mediatek,mtu3.txt | 74 ++++++++++++++++++++++++++ 1 file changed, 74 insertions(+) create mode 100644 doc/device-tree-bindings/usb/mediatek,mtu3.txt diff --git a/doc/device-tree-bindings/usb/mediatek,mtu3.txt b/doc/device-tree-bindings/usb/mediatek,mtu3.txt new file mode 100644 index 0000000..75a6785 --- /dev/null +++ b/doc/device-tree-bindings/usb/mediatek,mtu3.txt @@ -0,0 +1,74 @@ +The device node for Mediatek USB3.0 DRD controller + +Required properties: + - compatible : should be "mediatek,-mtu3", "mediatek,mtu3", + soc-model is the name of SoC, such as mt8512 etc, + when using "mediatek,mtu3" compatible string, you need SoC specific + ones in addition, one of: + - "mediatek,mt8512-mtu3" + - reg : specifies physical base address and size of the registers + - reg-names: should be + - "mac" : device IP, + - "ippc" : IP port control + - interrupts : interrupt used by the device IP + - power-domains : a phandle to USB power domain node to control USB's MTCMOS + - vusb33-supply : regulator of USB AVDD3.3v + - clocks : a list of phandle + clock-specifier pairs, one for each + entry in clock-names + - clock-names : must contain "sys_ck" for clock of controller, + the following clocks are optional: + "ref_ck", "mcu_ck" and "dma_ck"; + - phys : list of all the USB PHYs on this HCD + - dr_mode : should be one of "host", "peripheral" or "otg", + see : usb/generic.txt + +Optional properties: + - #address-cells, #size-cells : should be '2' if the device has sub-nodes + with 'reg' property + - ranges : allows valid 1:1 translation between child's address space and + parent's address space + - vbus-supply : reference to the VBUS regulator, needed when supports + dual-role mode. + - pinctrl-names : a pinctrl state named "default" is optional + - pinctrl-0 : pin control group + See: pinctrl/pinctrl-bindings.txt + + - maximum-speed : valid arguments are "full-speed", "high-speed", + "super-speed" and "super-speed-plus", + see: usb/generic.txt. + +Sub-nodes: +The xhci should be added as subnode to mtu3 as shown in the following example +if host mode is enabled. The DT binding details of xhci can be found in: + - usb/mediatek,mtk-xhci.txt + +Example: +ssusb: usb at 11271000 { + compatible = "mediatek,mt8173-mtu3", "mediatek,mtu3"; + reg = <0 0x11271000 0 0x3000>, + <0 0x11280700 0 0x0100>; + reg-names = "mac", "ippc"; + interrupts = ; + phys = <&phy_port0 PHY_TYPE_USB3>, + <&phy_port1 PHY_TYPE_USB2>; + power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>; + clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>; + clock-names = "sys_ck", "ref_ck"; + vusb33-supply = <&mt6397_vusb_reg>; + vbus-supply = <&usb_p0_vbus>; + dr_mode = "otg"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + usb_host: xhci at 11270000 { + compatible = "mediatek,mt8173-xhci", "mediatek,mtk-xhci"; + reg = <0 0x11270000 0 0x1000>; + reg-names = "mac"; + interrupts = ; + power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>; + clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>; + clock-names = "sys_ck", "ref_ck"; + vusb33-supply = <&mt6397_vusb_reg>; + }; +};