@@ -3,7 +3,7 @@ CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00200000
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_ENV_OFFSET=0x3F8000
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
CONFIG_SPL_TEXT_BASE=0xff8c2000
CONFIG_ROCKCHIP_RK3399=y
CONFIG_ROCKCHIP_BOOT_MODE_REG=0
@@ -40,6 +40,7 @@ CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_I2C_CROS_EC_TUNNEL=y
CONFIG_SYS_I2C_ROCKCHIP=y
@@ -53,6 +54,7 @@ CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_SF_DEFAULT_BUS=1
CONFIG_SF_DEFAULT_SPEED=20000000
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_DM_ETH=y
Update the config for chromebook_bob to support booting from SPI flash. The existing SPL size is too small since ATF is needed, so double it. Signed-off-by: Simon Glass <sjg at chromium.org> --- (no changes since v1) configs/chromebook_bob_defconfig | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)