diff mbox series

[3/4] mips: refactor disabling of caches

Message ID 20200711224557.612848-4-daniel.schwierzeck@gmail.com
State Accepted
Commit 60772433dd42987f3b965188d9577150084b8956
Headers show
Series MIPS: refactor and cleanup start.S (part 1) | expand

Commit Message

Daniel Schwierzeck July 11, 2020, 10:45 p.m. UTC 
Logically this code belongs to cache_init.S.

If a complex SoC needs to replace the generic cache init,
mips_cache_disable() can now be called from custom start.S files.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck at gmail.com>
---

 arch/mips/cpu/start.S      | 9 ++++-----
 arch/mips/lib/cache_init.S | 6 ++++++
 2 files changed, 10 insertions(+), 5 deletions(-)
diff mbox series

Patch

diff --git a/arch/mips/cpu/start.S b/arch/mips/cpu/start.S
index c3d1e64c1c..a9f8743717 100644
--- a/arch/mips/cpu/start.S
+++ b/arch/mips/cpu/start.S
@@ -196,11 +196,10 @@  wr_done:
 	mtc0	zero, CP0_COMPARE
 
 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
-	mfc0	t0, CP0_CONFIG
-	and	t0, t0, MIPS_CONF_IMPL
-	or	t0, t0, CONF_CM_UNCACHED
-	mtc0	t0, CP0_CONFIG
-	ehb
+	/* Disable caches */
+	PTR_LA	t9, mips_cache_disable
+	jalr	t9
+	 nop
 #endif
 
 #ifdef CONFIG_MIPS_CM
diff --git a/arch/mips/lib/cache_init.S b/arch/mips/lib/cache_init.S
index 2233d27137..602741c65d 100644
--- a/arch/mips/lib/cache_init.S
+++ b/arch/mips/lib/cache_init.S
@@ -418,6 +418,12 @@  return:
 	jr	R_RETURN
 	END(mips_cache_reset)
 
+LEAF(mips_cache_disable)
+	move	R_RETURN, ra
+	change_k0_cca_kseg1 CONF_CM_UNCACHED
+	jr	R_RETURN
+	END(mips_cache_disable)
+
 LEAF(change_k0_cca)
 	mfc0		t0, CP0_CONFIG
 #if __mips_isa_rev >= 2