[v2,48/49] x86: chromebook_panther: Correct the image layout

Message ID 20200613205717.v2.48.I1d5d0aedfd7b31070139796442d7280160cb8315@changeid
State Accepted
Commit 9589c447e82417dba6b6bf4ccd55d6d0f89ae1ef
Headers show
Series
  • rockchip: x86: Support building ROM files automatically with binman
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Commit Message

Simon Glass June 14, 2020, 2:57 a.m.
This board does not have microcode but at present that is not supported
by Kconfig nor the binman image layout. Fix both of these.

Signed-off-by: Simon Glass <sjg at chromium.org>
---

(no changes since v1)

 arch/x86/Kconfig                    | 7 ++++++-
 arch/x86/dts/u-boot.dtsi            | 6 +++++-
 configs/chromebox_panther_defconfig | 2 ++
 3 files changed, 13 insertions(+), 2 deletions(-)

Comments

Bin Meng June 29, 2020, 8:01 a.m. | #1
On Sun, Jun 14, 2020 at 10:58 AM Simon Glass <sjg at chromium.org> wrote:
>
> This board does not have microcode but at present that is not supported
> by Kconfig nor the binman image layout. Fix both of these.
>
> Signed-off-by: Simon Glass <sjg at chromium.org>
> ---
>
> (no changes since v1)
>
>  arch/x86/Kconfig                    | 7 ++++++-
>  arch/x86/dts/u-boot.dtsi            | 6 +++++-
>  configs/chromebox_panther_defconfig | 2 ++
>  3 files changed, 13 insertions(+), 2 deletions(-)
>

Reviewed-by: Bin Meng <bmeng.cn at gmail.com>

Patch

diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index c688c46475..6bea6b9b92 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -594,8 +594,13 @@  config HAVE_REFCODE
           Various peripherals may fail to work.
 
 config HAVE_MICROCODE
-	bool
+	bool "Board requires a microcode binary"
 	default y if !FSP_VERSION2
+	help
+	  Enable this if the board requires microcode to be loaded on boot.
+	  Typically this is handed by the FSP for modern boards, but for
+	  some older boards, it must be programmed by U-Boot, and that form
+	  part of the image.
 
 config SMP
 	bool "Enable Symmetric Multiprocessing"
diff --git a/arch/x86/dts/u-boot.dtsi b/arch/x86/dts/u-boot.dtsi
index 1e0a985b43..fa8106c8b8 100644
--- a/arch/x86/dts/u-boot.dtsi
+++ b/arch/x86/dts/u-boot.dtsi
@@ -75,11 +75,15 @@ 
 	u-boot {
 		offset = <CONFIG_SYS_TEXT_BASE>;
 	};
-# else
+# elif defined(CONFIG_HAVE_MICROCODE)
 	/* If there is no SPL then we need to put microcode in U-Boot */
 	u-boot-with-ucode-ptr {
 		offset = <CONFIG_X86_OFFSET_U_BOOT>;
 	};
+# else
+	u-boot-nodtb {
+		offset = <CONFIG_X86_OFFSET_U_BOOT>;
+	};
 # endif
 #endif
 #ifdef CONFIG_HAVE_MICROCODE
diff --git a/configs/chromebox_panther_defconfig b/configs/chromebox_panther_defconfig
index fd87ab262b..35ec3e912b 100644
--- a/configs/chromebox_panther_defconfig
+++ b/configs/chromebox_panther_defconfig
@@ -7,7 +7,9 @@  CONFIG_NR_DRAM_BANKS=8
 CONFIG_VENDOR_GOOGLE=y
 CONFIG_TARGET_CHROMEBOX_PANTHER=y
 CONFIG_HAVE_MRC=y
+# CONFIG_HAVE_MICROCODE is not set
 CONFIG_HAVE_VGA_BIOS=y
+CONFIG_X86_OFFSET_U_BOOT=0xffa00000
 CONFIG_FIT=y
 CONFIG_BOOTSTAGE=y
 CONFIG_BOOTSTAGE_REPORT=y