diff mbox series

[v1,6/8] spi: dw: Add mem_ops

Message ID c035a1f0-4a2f-3e59-78a8-3fe1c35c2b49@gmail.com
State New
Headers show
Series None | expand

Commit Message

Sean Anderson March 6, 2020, 9:20 p.m. UTC 
On 3/6/20 12:03 PM, Eugeniy Paltsev wrote:
> Hi Sean,
> 
> I've tested the SPI (with SPI flash) on HSDK board (which have DW SPI) with your changes.
> It completely break SPI on HSDK:
> 
> --------------------->8--------------------------
> # sf probe 
> unrecognized JEDEC id bytes: ff, ff, ff
> Failed to initialize SPI flash at 0:0 (error -2)
> --------------------->8--------------------------
> 
> Tested from maix_spi HEAD (e338571bf528f58b3ced7fbd0c1f5d923caa1cfd)
> 
> ---
>  Eugeniy Paltsev

Actually, it just occured to me that I did not add support for a gpio cs
to the xfer function, so it's likely that the chip is not enabling the
cs. Can you try testing with the following patch

---
 drivers/spi/designware_spi.c | 4 ++++
 1 file changed, 4 insertions(+)
diff mbox series

Patch

diff --git a/drivers/spi/designware_spi.c b/drivers/spi/designware_spi.c
index 298d1dbab5..a4e3dbd948 100644
--- a/drivers/spi/designware_spi.c
+++ b/drivers/spi/designware_spi.c
@@ -517,6 +517,8 @@  static int dw_spi_exec_op(struct spi_slave *slave, const struct spi_mem_op *op)
 	if (op->dummy.nbytes)
 		memset(op_buf + pos, 0xff, op->dummy.nbytes);
 
+	external_cs_manage(dev, false);
+
 	priv->tx = &op_buf;
 	priv->tx_end = priv->tx + op_len;
 	priv->rx = NULL;
@@ -586,6 +588,8 @@  static int dw_spi_exec_op(struct spi_slave *slave, const struct spi_mem_op *op)
 	}
 
 	dw_write(priv, DW_SPI_SER, 0);
+	external_cs_manage(dev, true);
+
 	debug("%s: %u bytes xfered\n", __func__, op->data.nbytes);
 	return ret;
 }