| Message ID | 20200311070320.21323-11-pragnesh.patel@sifive.com |
|---|---|
| State | New |
| Headers | show |
| Series | RISC-V SiFive FU540 support SPL | expand |
On Wed, Mar 11, 2020 at 3:04 PM Pragnesh Patel <pragnesh.patel at sifive.com> wrote: > > Add a support for SPL which will boot from L2 LIM (0x0800_0000) and > then boot U-boot FIT image including OpenSBI FW_DYNAMIC firmware nits: U-Boot > and U-Boot proper images from 1st partition of MMC boot devices. > > SPL related code is leverage from FSBL > (https://github.com/sifive/freedom-u540-c000-bootloader.git) > > Signed-off-by: Pragnesh Patel <pragnesh.patel at sifive.com> > --- > board/sifive/fu540/Kconfig | 8 +++ > board/sifive/fu540/Makefile | 4 ++ > board/sifive/fu540/fu540-memory-map.h | 23 ++++++++ > board/sifive/fu540/fu540.c | 24 +++++++++ > board/sifive/fu540/spl.c | 78 +++++++++++++++++++++++++++ > include/configs/sifive-fu540.h | 18 +++++++ > 6 files changed, 155 insertions(+) > create mode 100644 board/sifive/fu540/fu540-memory-map.h > create mode 100644 board/sifive/fu540/spl.c > > diff --git a/board/sifive/fu540/Kconfig b/board/sifive/fu540/Kconfig > index 900197bbb2..ebe3472f9a 100644 > --- a/board/sifive/fu540/Kconfig > +++ b/board/sifive/fu540/Kconfig > @@ -13,12 +13,20 @@ config SYS_CONFIG_NAME > default "sifive-fu540" > > config SYS_TEXT_BASE > + default 0x80200000 if SPL > default 0x80000000 if !RISCV_SMODE > default 0x80200000 if RISCV_SMODE > > +config SPL_TEXT_BASE > + default 0x08000000 > + > +config SPL_OPENSBI_LOAD_ADDR > + default 0x80000000 > + > config BOARD_SPECIFIC_OPTIONS # dummy > def_bool y > select GENERIC_RISCV > + select SUPPORT_SPL > imply CMD_DHCP > imply CMD_EXT2 > imply CMD_EXT4 > diff --git a/board/sifive/fu540/Makefile b/board/sifive/fu540/Makefile > index 6e1862c475..b05e2f5807 100644 > --- a/board/sifive/fu540/Makefile > +++ b/board/sifive/fu540/Makefile > @@ -3,3 +3,7 @@ > # Copyright (c) 2019 Western Digital Corporation or its affiliates. > > obj-y += fu540.o > + > +ifdef CONFIG_SPL_BUILD > +obj-y += spl.o > +endif > diff --git a/board/sifive/fu540/fu540-memory-map.h b/board/sifive/fu540/fu540-memory-map.h > new file mode 100644 > index 0000000000..cba464652b > --- /dev/null > +++ b/board/sifive/fu540/fu540-memory-map.h This file is not needed. See below. > @@ -0,0 +1,23 @@ > +/* SPDX-License-Identifier: GPL-2.0+ */ > +/* > + * Copyright (c) 2019 SiFive, Inc > + */ > + > +#ifndef FU540_MEMORY_MAP > +#define FU540_MEMORY_MAP > + > +#include <asm/arch/gpio.h> > + > +/**************************************************************************** > + * Platform definitions > + *****************************************************************************/ > + > +/* Memory map */ > +#define GPIO_CTRL_ADDR _AC(0x10060000, UL) > + > +/* Helper functions */ > +#define _REG32(p, i) (*(volatile uint32_t *)((p) + (i))) > + > +#define GPIO_REG(offset) _REG32(GPIO_CTRL_ADDR, offset) > + > +#endif /* FU540_MEMORY_MAP */ > diff --git a/board/sifive/fu540/fu540.c b/board/sifive/fu540/fu540.c > index 6c642b3082..89a65eb3fb 100644 > --- a/board/sifive/fu540/fu540.c > +++ b/board/sifive/fu540/fu540.c > @@ -11,6 +11,7 @@ > #include <linux/delay.h> > #include <linux/io.h> > #include <misc.h> > +#include <spl.h> > > /* > * This define is a value used for error/unknown serial. > @@ -114,3 +115,26 @@ int board_init(void) > > return 0; > } > + > +#ifdef CONFIG_SPL > +void board_boot_order(u32 *spl_boot_list) > +{ > + u8 i; > + u32 boot_devices[] = { > +#ifdef CONFIG_SPL_MMC_SUPPORT > + BOOT_DEVICE_MMC1, > +#endif > + }; > + > + for (i = 0; i < ARRAY_SIZE(boot_devices); i++) > + spl_boot_list[i] = boot_devices[i]; > +} > +#endif > + > +#ifdef CONFIG_SPL_LOAD_FIT > +int board_fit_config_name_match(const char *name) > +{ > + /* boot using first FIT config */ > + return 0; > +} > +#endif > diff --git a/board/sifive/fu540/spl.c b/board/sifive/fu540/spl.c > new file mode 100644 > index 0000000000..522bc24753 > --- /dev/null > +++ b/board/sifive/fu540/spl.c > @@ -0,0 +1,78 @@ > +// SPDX-License-Identifier: GPL-2.0+ > +/* > + * Copyright (c) 2019 SiFive, Inc > + * > + * Authors: > + * Pragnesh Patel <pragnesh.patel at sifive.com> > + */ > + > +#include <common.h> > +#include <spl.h> > +#include <misc.h> > +#include <dm.h> > + > +#include "fu540-memory-map.h" > + > +#define DDRCTLPLL_F 55 > +#define DDRCTLPLL_Q 2 These 2 macros are not needed. > + > +#define PHY_NRESET 0x1000 > + > +long nsec_per_cyc = 300; /* 33.333MHz */ > +void nsleep(long nsec) > +{ > + long step = nsec_per_cyc * 2; > + > + while (nsec > 0) > + nsec -= step; > +} > + > +void init_clk_and_ddr(void) > +{ > + int ret; > + struct udevice *dev; > + > + /* PRCI init */ > + ret = uclass_get_device(UCLASS_CLK, 0, &dev); > + if (ret) { > + debug("Clock init failed: %d\n", ret); > + return; > + } > + > + ret = uclass_get_device(UCLASS_RAM, 0, &dev); > + if (ret) { > + printf("DRAM init failed: %d\n", ret); > + return; > + } > + > + /* > + * GEMGXL init VSC8541 PHY reset sequence; > + * leave pull-down active for 2ms > + */ > + nsleep(2000000); > + /* Set GPIO 12 (PHY NRESET) to OE=1 and OVAL=1 */ > + GPIO_REG(GPIO_OUTPUT_VAL) |= PHY_NRESET; > + GPIO_REG(GPIO_OUTPUT_EN) |= PHY_NRESET; Please switch to use DM GPIO APIs to do the PHY reset. > + nsleep(100); > + > + /* Reset PHY again to enter unmanaged mode */ > + GPIO_REG(GPIO_OUTPUT_VAL) &= ~PHY_NRESET; > + nsleep(100); > + GPIO_REG(GPIO_OUTPUT_VAL) |= PHY_NRESET; > + nsleep(15000000); > +} > + > +void board_init_f(ulong dummy) > +{ > + int ret; > + > + ret = spl_early_init(); > + if (ret) > + panic("spl_early_init() failed: %d\n", ret); > + > + arch_cpu_init_dm(); > + > + init_clk_and_ddr(); > + > + preloader_console_init(); > +} > diff --git a/include/configs/sifive-fu540.h b/include/configs/sifive-fu540.h > index 2756ed5a77..ef3ae9b650 100644 > --- a/include/configs/sifive-fu540.h > +++ b/include/configs/sifive-fu540.h > @@ -11,6 +11,22 @@ > > #include <linux/sizes.h> > > +#ifdef CONFIG_SPL > + > +#define CONFIG_SPL_MAX_SIZE 0x00100000 > +#define CONFIG_SPL_BSS_START_ADDR 0x85000000 > +#define CONFIG_SPL_BSS_MAX_SIZE 0x00100000 > +#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ > + CONFIG_SPL_BSS_MAX_SIZE) > +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000 > + > +#define CONFIG_SPL_LOAD_FIT_ADDRESS 0x84000000 > + > +#define CONFIG_SPL_STACK (0x08000000 + 0x001D0000 - \ > + GENERATED_GBL_DATA_SIZE) > + > +#endif > + > #define CONFIG_SYS_SDRAM_BASE 0x80000000 > #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_2M) > > @@ -24,6 +40,7 @@ > > /* Environment options */ > > +#ifndef CONFIG_SPL_BUILD > #define BOOT_TARGET_DEVICES(func) \ > func(MMC, mmc, 0) \ > func(DHCP, dhcp, na) > @@ -43,5 +60,6 @@ > #define CONFIG_PREBOOT \ > "setenv fdt_addr ${fdtcontroladdr};" \ > "fdt addr ${fdtcontroladdr};" > +#endif > > #endif /* __CONFIG_H */ > -- Regards, Bin
On Wed, Mar 11, 2020 at 3:04 PM Pragnesh Patel <pragnesh.patel at sifive.com> wrote: > > Add a support for SPL which will boot from L2 LIM (0x0800_0000) and > then boot U-boot FIT image including OpenSBI FW_DYNAMIC firmware > and U-Boot proper images from 1st partition of MMC boot devices. > > SPL related code is leverage from FSBL > (https://github.com/sifive/freedom-u540-c000-bootloader.git) > > Signed-off-by: Pragnesh Patel <pragnesh.patel at sifive.com> > --- > board/sifive/fu540/Kconfig | 8 +++ > board/sifive/fu540/Makefile | 4 ++ > board/sifive/fu540/fu540-memory-map.h | 23 ++++++++ > board/sifive/fu540/fu540.c | 24 +++++++++ > board/sifive/fu540/spl.c | 78 +++++++++++++++++++++++++++ > include/configs/sifive-fu540.h | 18 +++++++ > 6 files changed, 155 insertions(+) > create mode 100644 board/sifive/fu540/fu540-memory-map.h > create mode 100644 board/sifive/fu540/spl.c > > diff --git a/board/sifive/fu540/Kconfig b/board/sifive/fu540/Kconfig > index 900197bbb2..ebe3472f9a 100644 > --- a/board/sifive/fu540/Kconfig > +++ b/board/sifive/fu540/Kconfig > @@ -13,12 +13,20 @@ config SYS_CONFIG_NAME > default "sifive-fu540" > > config SYS_TEXT_BASE > + default 0x80200000 if SPL > default 0x80000000 if !RISCV_SMODE > default 0x80200000 if RISCV_SMODE > > +config SPL_TEXT_BASE > + default 0x08000000 > + > +config SPL_OPENSBI_LOAD_ADDR > + default 0x80000000 > + > config BOARD_SPECIFIC_OPTIONS # dummy > def_bool y > select GENERIC_RISCV > + select SUPPORT_SPL > imply CMD_DHCP > imply CMD_EXT2 > imply CMD_EXT4 > diff --git a/board/sifive/fu540/Makefile b/board/sifive/fu540/Makefile > index 6e1862c475..b05e2f5807 100644 > --- a/board/sifive/fu540/Makefile > +++ b/board/sifive/fu540/Makefile > @@ -3,3 +3,7 @@ > # Copyright (c) 2019 Western Digital Corporation or its affiliates. > > obj-y += fu540.o > + > +ifdef CONFIG_SPL_BUILD > +obj-y += spl.o > +endif > diff --git a/board/sifive/fu540/fu540-memory-map.h b/board/sifive/fu540/fu540-memory-map.h > new file mode 100644 > index 0000000000..cba464652b > --- /dev/null > +++ b/board/sifive/fu540/fu540-memory-map.h > @@ -0,0 +1,23 @@ > +/* SPDX-License-Identifier: GPL-2.0+ */ > +/* > + * Copyright (c) 2019 SiFive, Inc > + */ > + > +#ifndef FU540_MEMORY_MAP > +#define FU540_MEMORY_MAP > + > +#include <asm/arch/gpio.h> > + > +/**************************************************************************** > + * Platform definitions > + *****************************************************************************/ > + > +/* Memory map */ > +#define GPIO_CTRL_ADDR _AC(0x10060000, UL) > + > +/* Helper functions */ > +#define _REG32(p, i) (*(volatile uint32_t *)((p) + (i))) > + > +#define GPIO_REG(offset) _REG32(GPIO_CTRL_ADDR, offset) > + > +#endif /* FU540_MEMORY_MAP */ > diff --git a/board/sifive/fu540/fu540.c b/board/sifive/fu540/fu540.c > index 6c642b3082..89a65eb3fb 100644 > --- a/board/sifive/fu540/fu540.c > +++ b/board/sifive/fu540/fu540.c > @@ -11,6 +11,7 @@ > #include <linux/delay.h> > #include <linux/io.h> > #include <misc.h> > +#include <spl.h> > > /* > * This define is a value used for error/unknown serial. > @@ -114,3 +115,26 @@ int board_init(void) > > return 0; > } > + > +#ifdef CONFIG_SPL > +void board_boot_order(u32 *spl_boot_list) > +{ > + u8 i; > + u32 boot_devices[] = { > +#ifdef CONFIG_SPL_MMC_SUPPORT > + BOOT_DEVICE_MMC1, > +#endif > + }; > + > + for (i = 0; i < ARRAY_SIZE(boot_devices); i++) > + spl_boot_list[i] = boot_devices[i]; > +} > +#endif > + > +#ifdef CONFIG_SPL_LOAD_FIT > +int board_fit_config_name_match(const char *name) > +{ > + /* boot using first FIT config */ > + return 0; > +} > +#endif > diff --git a/board/sifive/fu540/spl.c b/board/sifive/fu540/spl.c > new file mode 100644 > index 0000000000..522bc24753 > --- /dev/null > +++ b/board/sifive/fu540/spl.c > @@ -0,0 +1,78 @@ > +// SPDX-License-Identifier: GPL-2.0+ > +/* > + * Copyright (c) 2019 SiFive, Inc > + * > + * Authors: > + * Pragnesh Patel <pragnesh.patel at sifive.com> > + */ > + > +#include <common.h> > +#include <spl.h> > +#include <misc.h> > +#include <dm.h> > + > +#include "fu540-memory-map.h" > + > +#define DDRCTLPLL_F 55 > +#define DDRCTLPLL_Q 2 > + > +#define PHY_NRESET 0x1000 > + > +long nsec_per_cyc = 300; /* 33.333MHz */ > +void nsleep(long nsec) > +{ > + long step = nsec_per_cyc * 2; > + > + while (nsec > 0) > + nsec -= step; > +} > + > +void init_clk_and_ddr(void) > +{ > + int ret; > + struct udevice *dev; > + > + /* PRCI init */ > + ret = uclass_get_device(UCLASS_CLK, 0, &dev); > + if (ret) { > + debug("Clock init failed: %d\n", ret); > + return; > + } > + > + ret = uclass_get_device(UCLASS_RAM, 0, &dev); > + if (ret) { > + printf("DRAM init failed: %d\n", ret); > + return; > + } > + This should be split into two parts: SoC specific parts should go to arch/riscv/fu540/spl.c, and board specific parts remain here. Otherwise it's hard to re-use the same SPL codes for another board built on top of fu540. > + /* > + * GEMGXL init VSC8541 PHY reset sequence; > + * leave pull-down active for 2ms > + */ > + nsleep(2000000); > + /* Set GPIO 12 (PHY NRESET) to OE=1 and OVAL=1 */ > + GPIO_REG(GPIO_OUTPUT_VAL) |= PHY_NRESET; > + GPIO_REG(GPIO_OUTPUT_EN) |= PHY_NRESET; > + nsleep(100); > + > + /* Reset PHY again to enter unmanaged mode */ > + GPIO_REG(GPIO_OUTPUT_VAL) &= ~PHY_NRESET; > + nsleep(100); > + GPIO_REG(GPIO_OUTPUT_VAL) |= PHY_NRESET; > + nsleep(15000000); > +} > + > +void board_init_f(ulong dummy) > +{ > + int ret; > + > + ret = spl_early_init(); > + if (ret) > + panic("spl_early_init() failed: %d\n", ret); > + > + arch_cpu_init_dm(); > + > + init_clk_and_ddr(); > + > + preloader_console_init(); > +} Regards, Bin
Hi Bin, >-----Original Message----- >From: Bin Meng <bmeng.cn at gmail.com> >Sent: 13 March 2020 13:58 >To: Pragnesh Patel <pragnesh.patel at sifive.com> >Cc: U-Boot Mailing List <u-boot at lists.denx.de>; Atish Patra ><atish.patra at wdc.com>; Palmer Dabbelt <palmerdabbelt at google.com>; Paul >Walmsley <paul.walmsley at sifive.com>; Jagan Teki ><jagan at amarulasolutions.com>; Troy Benjegerdes ><troy.benjegerdes at sifive.com>; Anup Patel <anup.patel at wdc.com>; Sagar >Kadam <sagar.kadam at sifive.com>; Rick Chen <rick at andestech.com>; Palmer >Dabbelt <palmer at dabbelt.com> >Subject: Re: [PATCH v5 10/14] riscv: sifive: fu540: add SPL configuration > >On Wed, Mar 11, 2020 at 3:04 PM Pragnesh Patel ><pragnesh.patel at sifive.com> wrote: >> >> Add a support for SPL which will boot from L2 LIM (0x0800_0000) and >> then boot U-boot FIT image including OpenSBI FW_DYNAMIC firmware > >nits: U-Boot Will update in v6. > >> and U-Boot proper images from 1st partition of MMC boot devices. >> >> SPL related code is leverage from FSBL >> (https://github.com/sifive/freedom-u540-c000-bootloader.git) >> >> Signed-off-by: Pragnesh Patel <pragnesh.patel at sifive.com> >> --- >> board/sifive/fu540/Kconfig | 8 +++ >> board/sifive/fu540/Makefile | 4 ++ >> board/sifive/fu540/fu540-memory-map.h | 23 ++++++++ >> board/sifive/fu540/fu540.c | 24 +++++++++ >> board/sifive/fu540/spl.c | 78 +++++++++++++++++++++++++++ >> include/configs/sifive-fu540.h | 18 +++++++ >> 6 files changed, 155 insertions(+) >> create mode 100644 board/sifive/fu540/fu540-memory-map.h >> create mode 100644 board/sifive/fu540/spl.c >> >> diff --git a/board/sifive/fu540/Kconfig b/board/sifive/fu540/Kconfig >> index 900197bbb2..ebe3472f9a 100644 >> --- a/board/sifive/fu540/Kconfig >> +++ b/board/sifive/fu540/Kconfig >> @@ -13,12 +13,20 @@ config SYS_CONFIG_NAME >> default "sifive-fu540" >> >> config SYS_TEXT_BASE >> + default 0x80200000 if SPL >> default 0x80000000 if !RISCV_SMODE >> default 0x80200000 if RISCV_SMODE >> >> +config SPL_TEXT_BASE >> + default 0x08000000 >> + >> +config SPL_OPENSBI_LOAD_ADDR >> + default 0x80000000 >> + >> config BOARD_SPECIFIC_OPTIONS # dummy >> def_bool y >> select GENERIC_RISCV >> + select SUPPORT_SPL >> imply CMD_DHCP >> imply CMD_EXT2 >> imply CMD_EXT4 >> diff --git a/board/sifive/fu540/Makefile b/board/sifive/fu540/Makefile >> index 6e1862c475..b05e2f5807 100644 >> --- a/board/sifive/fu540/Makefile >> +++ b/board/sifive/fu540/Makefile >> @@ -3,3 +3,7 @@ >> # Copyright (c) 2019 Western Digital Corporation or its affiliates. >> >> obj-y += fu540.o >> + >> +ifdef CONFIG_SPL_BUILD >> +obj-y += spl.o >> +endif >> diff --git a/board/sifive/fu540/fu540-memory-map.h >> b/board/sifive/fu540/fu540-memory-map.h >> new file mode 100644 >> index 0000000000..cba464652b >> --- /dev/null >> +++ b/board/sifive/fu540/fu540-memory-map.h > >This file is not needed. See below. > >> @@ -0,0 +1,23 @@ >> +/* SPDX-License-Identifier: GPL-2.0+ */ >> +/* >> + * Copyright (c) 2019 SiFive, Inc >> + */ >> + >> +#ifndef FU540_MEMORY_MAP >> +#define FU540_MEMORY_MAP >> + >> +#include <asm/arch/gpio.h> >> + >> >+/*************************************************************** >***** >> +******** >> + * Platform definitions >> + >> >+**************************************************************** >***** >> +********/ >> + >> +/* Memory map */ >> +#define GPIO_CTRL_ADDR _AC(0x10060000, UL) >> + >> +/* Helper functions */ >> +#define _REG32(p, i) (*(volatile uint32_t *)((p) + (i))) >> + >> +#define GPIO_REG(offset) _REG32(GPIO_CTRL_ADDR, offset) >> + >> +#endif /* FU540_MEMORY_MAP */ >> diff --git a/board/sifive/fu540/fu540.c b/board/sifive/fu540/fu540.c >> index 6c642b3082..89a65eb3fb 100644 >> --- a/board/sifive/fu540/fu540.c >> +++ b/board/sifive/fu540/fu540.c >> @@ -11,6 +11,7 @@ >> #include <linux/delay.h> >> #include <linux/io.h> >> #include <misc.h> >> +#include <spl.h> >> >> /* >> * This define is a value used for error/unknown serial. >> @@ -114,3 +115,26 @@ int board_init(void) >> >> return 0; >> } >> + >> +#ifdef CONFIG_SPL >> +void board_boot_order(u32 *spl_boot_list) { >> + u8 i; >> + u32 boot_devices[] = { >> +#ifdef CONFIG_SPL_MMC_SUPPORT >> + BOOT_DEVICE_MMC1, >> +#endif >> + }; >> + >> + for (i = 0; i < ARRAY_SIZE(boot_devices); i++) >> + spl_boot_list[i] = boot_devices[i]; } #endif >> + >> +#ifdef CONFIG_SPL_LOAD_FIT >> +int board_fit_config_name_match(const char *name) { >> + /* boot using first FIT config */ >> + return 0; >> +} >> +#endif >> diff --git a/board/sifive/fu540/spl.c b/board/sifive/fu540/spl.c new >> file mode 100644 index 0000000000..522bc24753 >> --- /dev/null >> +++ b/board/sifive/fu540/spl.c >> @@ -0,0 +1,78 @@ >> +// SPDX-License-Identifier: GPL-2.0+ >> +/* >> + * Copyright (c) 2019 SiFive, Inc >> + * >> + * Authors: >> + * Pragnesh Patel <pragnesh.patel at sifive.com> >> + */ >> + >> +#include <common.h> >> +#include <spl.h> >> +#include <misc.h> >> +#include <dm.h> >> + >> +#include "fu540-memory-map.h" >> + >> +#define DDRCTLPLL_F 55 >> +#define DDRCTLPLL_Q 2 > >These 2 macros are not needed. Will remove in v6, thanks for highlighting this. > >> + >> +#define PHY_NRESET 0x1000 >> + >> +long nsec_per_cyc = 300; /* 33.333MHz */ void nsleep(long nsec) { >> + long step = nsec_per_cyc * 2; >> + >> + while (nsec > 0) >> + nsec -= step; >> +} >> + >> +void init_clk_and_ddr(void) >> +{ >> + int ret; >> + struct udevice *dev; >> + >> + /* PRCI init */ >> + ret = uclass_get_device(UCLASS_CLK, 0, &dev); >> + if (ret) { >> + debug("Clock init failed: %d\n", ret); >> + return; >> + } >> + >> + ret = uclass_get_device(UCLASS_RAM, 0, &dev); >> + if (ret) { >> + printf("DRAM init failed: %d\n", ret); >> + return; >> + } >> + >> + /* >> + * GEMGXL init VSC8541 PHY reset sequence; >> + * leave pull-down active for 2ms >> + */ >> + nsleep(2000000); >> + /* Set GPIO 12 (PHY NRESET) to OE=1 and OVAL=1 */ >> + GPIO_REG(GPIO_OUTPUT_VAL) |= PHY_NRESET; >> + GPIO_REG(GPIO_OUTPUT_EN) |= PHY_NRESET; > >Please switch to use DM GPIO APIs to do the PHY reset. Will update in v6. > >> + nsleep(100); >> + >> + /* Reset PHY again to enter unmanaged mode */ >> + GPIO_REG(GPIO_OUTPUT_VAL) &= ~PHY_NRESET; >> + nsleep(100); >> + GPIO_REG(GPIO_OUTPUT_VAL) |= PHY_NRESET; >> + nsleep(15000000); >> +} >> + >> +void board_init_f(ulong dummy) >> +{ >> + int ret; >> + >> + ret = spl_early_init(); >> + if (ret) >> + panic("spl_early_init() failed: %d\n", ret); >> + >> + arch_cpu_init_dm(); >> + >> + init_clk_and_ddr(); >> + >> + preloader_console_init(); >> +} >> diff --git a/include/configs/sifive-fu540.h >> b/include/configs/sifive-fu540.h index 2756ed5a77..ef3ae9b650 100644 >> --- a/include/configs/sifive-fu540.h >> +++ b/include/configs/sifive-fu540.h >> @@ -11,6 +11,22 @@ >> >> #include <linux/sizes.h> >> >> +#ifdef CONFIG_SPL >> + >> +#define CONFIG_SPL_MAX_SIZE 0x00100000 >> +#define CONFIG_SPL_BSS_START_ADDR 0x85000000 >> +#define CONFIG_SPL_BSS_MAX_SIZE 0x00100000 >> +#define CONFIG_SYS_SPL_MALLOC_START >(CONFIG_SPL_BSS_START_ADDR + \ >> + CONFIG_SPL_BSS_MAX_SIZE) >> +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000 >> + >> +#define CONFIG_SPL_LOAD_FIT_ADDRESS 0x84000000 >> + >> +#define CONFIG_SPL_STACK (0x08000000 + 0x001D0000 - \ >> + GENERATED_GBL_DATA_SIZE) >> + >> +#endif >> + >> #define CONFIG_SYS_SDRAM_BASE 0x80000000 >> #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + >SZ_2M) >> >> @@ -24,6 +40,7 @@ >> >> /* Environment options */ >> >> +#ifndef CONFIG_SPL_BUILD >> #define BOOT_TARGET_DEVICES(func) \ >> func(MMC, mmc, 0) \ >> func(DHCP, dhcp, na) >> @@ -43,5 +60,6 @@ >> #define CONFIG_PREBOOT \ >> "setenv fdt_addr ${fdtcontroladdr};" \ >> "fdt addr ${fdtcontroladdr};" >> +#endif >> >> #endif /* __CONFIG_H */ >> -- > >Regards, >Bin
Hi Bin, >-----Original Message----- >From: Bin Meng <bmeng.cn at gmail.com> >Sent: 13 March 2020 19:29 >To: Pragnesh Patel <pragnesh.patel at sifive.com> >Cc: U-Boot Mailing List <u-boot at lists.denx.de>; Atish Patra ><atish.patra at wdc.com>; Palmer Dabbelt <palmerdabbelt at google.com>; Paul >Walmsley <paul.walmsley at sifive.com>; Jagan Teki ><jagan at amarulasolutions.com>; Troy Benjegerdes ><troy.benjegerdes at sifive.com>; Anup Patel <anup.patel at wdc.com>; Sagar >Kadam <sagar.kadam at sifive.com>; Rick Chen <rick at andestech.com>; Palmer >Dabbelt <palmer at dabbelt.com> >Subject: Re: [PATCH v5 10/14] riscv: sifive: fu540: add SPL configuration > >On Wed, Mar 11, 2020 at 3:04 PM Pragnesh Patel ><pragnesh.patel at sifive.com> wrote: >> >> Add a support for SPL which will boot from L2 LIM (0x0800_0000) and >> then boot U-boot FIT image including OpenSBI FW_DYNAMIC firmware and >> U-Boot proper images from 1st partition of MMC boot devices. >> >> SPL related code is leverage from FSBL >> (https://github.com/sifive/freedom-u540-c000-bootloader.git) >> >> Signed-off-by: Pragnesh Patel <pragnesh.patel at sifive.com> >> --- >> board/sifive/fu540/Kconfig | 8 +++ >> board/sifive/fu540/Makefile | 4 ++ >> board/sifive/fu540/fu540-memory-map.h | 23 ++++++++ >> board/sifive/fu540/fu540.c | 24 +++++++++ >> board/sifive/fu540/spl.c | 78 +++++++++++++++++++++++++++ >> include/configs/sifive-fu540.h | 18 +++++++ >> 6 files changed, 155 insertions(+) >> create mode 100644 board/sifive/fu540/fu540-memory-map.h >> create mode 100644 board/sifive/fu540/spl.c >> >> diff --git a/board/sifive/fu540/Kconfig b/board/sifive/fu540/Kconfig >> index 900197bbb2..ebe3472f9a 100644 >> --- a/board/sifive/fu540/Kconfig >> +++ b/board/sifive/fu540/Kconfig >> @@ -13,12 +13,20 @@ config SYS_CONFIG_NAME >> default "sifive-fu540" >> >> config SYS_TEXT_BASE >> + default 0x80200000 if SPL >> default 0x80000000 if !RISCV_SMODE >> default 0x80200000 if RISCV_SMODE >> >> +config SPL_TEXT_BASE >> + default 0x08000000 >> + >> +config SPL_OPENSBI_LOAD_ADDR >> + default 0x80000000 >> + >> config BOARD_SPECIFIC_OPTIONS # dummy >> def_bool y >> select GENERIC_RISCV >> + select SUPPORT_SPL >> imply CMD_DHCP >> imply CMD_EXT2 >> imply CMD_EXT4 >> diff --git a/board/sifive/fu540/Makefile b/board/sifive/fu540/Makefile >> index 6e1862c475..b05e2f5807 100644 >> --- a/board/sifive/fu540/Makefile >> +++ b/board/sifive/fu540/Makefile >> @@ -3,3 +3,7 @@ >> # Copyright (c) 2019 Western Digital Corporation or its affiliates. >> >> obj-y += fu540.o >> + >> +ifdef CONFIG_SPL_BUILD >> +obj-y += spl.o >> +endif >> diff --git a/board/sifive/fu540/fu540-memory-map.h >> b/board/sifive/fu540/fu540-memory-map.h >> new file mode 100644 >> index 0000000000..cba464652b >> --- /dev/null >> +++ b/board/sifive/fu540/fu540-memory-map.h >> @@ -0,0 +1,23 @@ >> +/* SPDX-License-Identifier: GPL-2.0+ */ >> +/* >> + * Copyright (c) 2019 SiFive, Inc >> + */ >> + >> +#ifndef FU540_MEMORY_MAP >> +#define FU540_MEMORY_MAP >> + >> +#include <asm/arch/gpio.h> >> + >> >+/*************************************************************** >***** >> +******** >> + * Platform definitions >> + >> >+**************************************************************** >***** >> +********/ >> + >> +/* Memory map */ >> +#define GPIO_CTRL_ADDR _AC(0x10060000, UL) >> + >> +/* Helper functions */ >> +#define _REG32(p, i) (*(volatile uint32_t *)((p) + (i))) >> + >> +#define GPIO_REG(offset) _REG32(GPIO_CTRL_ADDR, offset) >> + >> +#endif /* FU540_MEMORY_MAP */ >> diff --git a/board/sifive/fu540/fu540.c b/board/sifive/fu540/fu540.c >> index 6c642b3082..89a65eb3fb 100644 >> --- a/board/sifive/fu540/fu540.c >> +++ b/board/sifive/fu540/fu540.c >> @@ -11,6 +11,7 @@ >> #include <linux/delay.h> >> #include <linux/io.h> >> #include <misc.h> >> +#include <spl.h> >> >> /* >> * This define is a value used for error/unknown serial. >> @@ -114,3 +115,26 @@ int board_init(void) >> >> return 0; >> } >> + >> +#ifdef CONFIG_SPL >> +void board_boot_order(u32 *spl_boot_list) { >> + u8 i; >> + u32 boot_devices[] = { >> +#ifdef CONFIG_SPL_MMC_SUPPORT >> + BOOT_DEVICE_MMC1, >> +#endif >> + }; >> + >> + for (i = 0; i < ARRAY_SIZE(boot_devices); i++) >> + spl_boot_list[i] = boot_devices[i]; } #endif >> + >> +#ifdef CONFIG_SPL_LOAD_FIT >> +int board_fit_config_name_match(const char *name) { >> + /* boot using first FIT config */ >> + return 0; >> +} >> +#endif >> diff --git a/board/sifive/fu540/spl.c b/board/sifive/fu540/spl.c new >> file mode 100644 index 0000000000..522bc24753 >> --- /dev/null >> +++ b/board/sifive/fu540/spl.c >> @@ -0,0 +1,78 @@ >> +// SPDX-License-Identifier: GPL-2.0+ >> +/* >> + * Copyright (c) 2019 SiFive, Inc >> + * >> + * Authors: >> + * Pragnesh Patel <pragnesh.patel at sifive.com> >> + */ >> + >> +#include <common.h> >> +#include <spl.h> >> +#include <misc.h> >> +#include <dm.h> >> + >> +#include "fu540-memory-map.h" >> + >> +#define DDRCTLPLL_F 55 >> +#define DDRCTLPLL_Q 2 >> + >> +#define PHY_NRESET 0x1000 >> + >> +long nsec_per_cyc = 300; /* 33.333MHz */ void nsleep(long nsec) { >> + long step = nsec_per_cyc * 2; >> + >> + while (nsec > 0) >> + nsec -= step; >> +} >> + >> +void init_clk_and_ddr(void) >> +{ >> + int ret; >> + struct udevice *dev; >> + >> + /* PRCI init */ >> + ret = uclass_get_device(UCLASS_CLK, 0, &dev); >> + if (ret) { >> + debug("Clock init failed: %d\n", ret); >> + return; >> + } >> + >> + ret = uclass_get_device(UCLASS_RAM, 0, &dev); >> + if (ret) { >> + printf("DRAM init failed: %d\n", ret); >> + return; >> + } >> + > >This should be split into two parts: > >SoC specific parts should go to arch/riscv/fu540/spl.c, and board specific parts >remain here. > >Otherwise it's hard to re-use the same SPL codes for another board built on >top of fu540. Yes, you are right. Let me clear this. PRCI and RAM initialization will go to arch/riscv/fu540/spl.c and VSC8541 PHY reset should be in board/Sifive/fu540/spl.c > >> + /* >> + * GEMGXL init VSC8541 PHY reset sequence; >> + * leave pull-down active for 2ms >> + */ >> + nsleep(2000000); >> + /* Set GPIO 12 (PHY NRESET) to OE=1 and OVAL=1 */ >> + GPIO_REG(GPIO_OUTPUT_VAL) |= PHY_NRESET; >> + GPIO_REG(GPIO_OUTPUT_EN) |= PHY_NRESET; >> + nsleep(100); >> + >> + /* Reset PHY again to enter unmanaged mode */ >> + GPIO_REG(GPIO_OUTPUT_VAL) &= ~PHY_NRESET; >> + nsleep(100); >> + GPIO_REG(GPIO_OUTPUT_VAL) |= PHY_NRESET; >> + nsleep(15000000); >> +} >> + >> +void board_init_f(ulong dummy) >> +{ >> + int ret; >> + >> + ret = spl_early_init(); >> + if (ret) >> + panic("spl_early_init() failed: %d\n", ret); >> + >> + arch_cpu_init_dm(); >> + >> + init_clk_and_ddr(); >> + >> + preloader_console_init(); >> +} > >Regards, >Bin
diff --git a/board/sifive/fu540/Kconfig b/board/sifive/fu540/Kconfig index 900197bbb2..ebe3472f9a 100644 --- a/board/sifive/fu540/Kconfig +++ b/board/sifive/fu540/Kconfig @@ -13,12 +13,20 @@ config SYS_CONFIG_NAME default "sifive-fu540" config SYS_TEXT_BASE + default 0x80200000 if SPL default 0x80000000 if !RISCV_SMODE default 0x80200000 if RISCV_SMODE +config SPL_TEXT_BASE + default 0x08000000 + +config SPL_OPENSBI_LOAD_ADDR + default 0x80000000 + config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select GENERIC_RISCV + select SUPPORT_SPL imply CMD_DHCP imply CMD_EXT2 imply CMD_EXT4 diff --git a/board/sifive/fu540/Makefile b/board/sifive/fu540/Makefile index 6e1862c475..b05e2f5807 100644 --- a/board/sifive/fu540/Makefile +++ b/board/sifive/fu540/Makefile @@ -3,3 +3,7 @@ # Copyright (c) 2019 Western Digital Corporation or its affiliates. obj-y += fu540.o + +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +endif diff --git a/board/sifive/fu540/fu540-memory-map.h b/board/sifive/fu540/fu540-memory-map.h new file mode 100644 index 0000000000..cba464652b --- /dev/null +++ b/board/sifive/fu540/fu540-memory-map.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2019 SiFive, Inc + */ + +#ifndef FU540_MEMORY_MAP +#define FU540_MEMORY_MAP + +#include <asm/arch/gpio.h> + +/**************************************************************************** + * Platform definitions + *****************************************************************************/ + +/* Memory map */ +#define GPIO_CTRL_ADDR _AC(0x10060000, UL) + +/* Helper functions */ +#define _REG32(p, i) (*(volatile uint32_t *)((p) + (i))) + +#define GPIO_REG(offset) _REG32(GPIO_CTRL_ADDR, offset) + +#endif /* FU540_MEMORY_MAP */ diff --git a/board/sifive/fu540/fu540.c b/board/sifive/fu540/fu540.c index 6c642b3082..89a65eb3fb 100644 --- a/board/sifive/fu540/fu540.c +++ b/board/sifive/fu540/fu540.c @@ -11,6 +11,7 @@ #include <linux/delay.h> #include <linux/io.h> #include <misc.h> +#include <spl.h> /* * This define is a value used for error/unknown serial. @@ -114,3 +115,26 @@ int board_init(void) return 0; } + +#ifdef CONFIG_SPL +void board_boot_order(u32 *spl_boot_list) +{ + u8 i; + u32 boot_devices[] = { +#ifdef CONFIG_SPL_MMC_SUPPORT + BOOT_DEVICE_MMC1, +#endif + }; + + for (i = 0; i < ARRAY_SIZE(boot_devices); i++) + spl_boot_list[i] = boot_devices[i]; +} +#endif + +#ifdef CONFIG_SPL_LOAD_FIT +int board_fit_config_name_match(const char *name) +{ + /* boot using first FIT config */ + return 0; +} +#endif diff --git a/board/sifive/fu540/spl.c b/board/sifive/fu540/spl.c new file mode 100644 index 0000000000..522bc24753 --- /dev/null +++ b/board/sifive/fu540/spl.c @@ -0,0 +1,78 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2019 SiFive, Inc + * + * Authors: + * Pragnesh Patel <pragnesh.patel at sifive.com> + */ + +#include <common.h> +#include <spl.h> +#include <misc.h> +#include <dm.h> + +#include "fu540-memory-map.h" + +#define DDRCTLPLL_F 55 +#define DDRCTLPLL_Q 2 + +#define PHY_NRESET 0x1000 + +long nsec_per_cyc = 300; /* 33.333MHz */ +void nsleep(long nsec) +{ + long step = nsec_per_cyc * 2; + + while (nsec > 0) + nsec -= step; +} + +void init_clk_and_ddr(void) +{ + int ret; + struct udevice *dev; + + /* PRCI init */ + ret = uclass_get_device(UCLASS_CLK, 0, &dev); + if (ret) { + debug("Clock init failed: %d\n", ret); + return; + } + + ret = uclass_get_device(UCLASS_RAM, 0, &dev); + if (ret) { + printf("DRAM init failed: %d\n", ret); + return; + } + + /* + * GEMGXL init VSC8541 PHY reset sequence; + * leave pull-down active for 2ms + */ + nsleep(2000000); + /* Set GPIO 12 (PHY NRESET) to OE=1 and OVAL=1 */ + GPIO_REG(GPIO_OUTPUT_VAL) |= PHY_NRESET; + GPIO_REG(GPIO_OUTPUT_EN) |= PHY_NRESET; + nsleep(100); + + /* Reset PHY again to enter unmanaged mode */ + GPIO_REG(GPIO_OUTPUT_VAL) &= ~PHY_NRESET; + nsleep(100); + GPIO_REG(GPIO_OUTPUT_VAL) |= PHY_NRESET; + nsleep(15000000); +} + +void board_init_f(ulong dummy) +{ + int ret; + + ret = spl_early_init(); + if (ret) + panic("spl_early_init() failed: %d\n", ret); + + arch_cpu_init_dm(); + + init_clk_and_ddr(); + + preloader_console_init(); +} diff --git a/include/configs/sifive-fu540.h b/include/configs/sifive-fu540.h index 2756ed5a77..ef3ae9b650 100644 --- a/include/configs/sifive-fu540.h +++ b/include/configs/sifive-fu540.h @@ -11,6 +11,22 @@ #include <linux/sizes.h> +#ifdef CONFIG_SPL + +#define CONFIG_SPL_MAX_SIZE 0x00100000 +#define CONFIG_SPL_BSS_START_ADDR 0x85000000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x00100000 +#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ + CONFIG_SPL_BSS_MAX_SIZE) +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000 + +#define CONFIG_SPL_LOAD_FIT_ADDRESS 0x84000000 + +#define CONFIG_SPL_STACK (0x08000000 + 0x001D0000 - \ + GENERATED_GBL_DATA_SIZE) + +#endif + #define CONFIG_SYS_SDRAM_BASE 0x80000000 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_2M) @@ -24,6 +40,7 @@ /* Environment options */ +#ifndef CONFIG_SPL_BUILD #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) \ func(DHCP, dhcp, na) @@ -43,5 +60,6 @@ #define CONFIG_PREBOOT \ "setenv fdt_addr ${fdtcontroladdr};" \ "fdt addr ${fdtcontroladdr};" +#endif #endif /* __CONFIG_H */
Add a support for SPL which will boot from L2 LIM (0x0800_0000) and then boot U-boot FIT image including OpenSBI FW_DYNAMIC firmware and U-Boot proper images from 1st partition of MMC boot devices. SPL related code is leverage from FSBL (https://github.com/sifive/freedom-u540-c000-bootloader.git) Signed-off-by: Pragnesh Patel <pragnesh.patel at sifive.com> --- board/sifive/fu540/Kconfig | 8 +++ board/sifive/fu540/Makefile | 4 ++ board/sifive/fu540/fu540-memory-map.h | 23 ++++++++ board/sifive/fu540/fu540.c | 24 +++++++++ board/sifive/fu540/spl.c | 78 +++++++++++++++++++++++++++ include/configs/sifive-fu540.h | 18 +++++++ 6 files changed, 155 insertions(+) create mode 100644 board/sifive/fu540/fu540-memory-map.h create mode 100644 board/sifive/fu540/spl.c