diff mbox series

[11/12] board: fsl: ls2080a: Initialize the GIC redistributor tables

Message ID 20200319053846.2304-12-Zhiqiang.Hou@nxp.com
State New
Headers show
Series fsl: layerscape: Initialize the GIC redistributor | expand

Commit Message

Zhiqiang Hou March 19, 2020, 5:38 a.m. UTC 
From: Hou Zhiqiang <Zhiqiang.Hou at nxp.com>

Fixup kernel DT to reserve memory for GIC redistributor tables,
and initialize the redistributor configuration and pending
tables using the reserved memory.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou at nxp.com>
---
 board/freescale/ls2080aqds/ls2080aqds.c | 14 ++++++++++++++
 board/freescale/ls2080ardb/ls2080ardb.c | 14 ++++++++++++++
 2 files changed, 28 insertions(+)

Comments

Bin Meng March 19, 2020, 11:56 a.m. UTC | #1 
On Thu, Mar 19, 2020 at 1:44 PM Zhiqiang Hou <Zhiqiang.Hou at nxp.com> wrote:
>
> From: Hou Zhiqiang <Zhiqiang.Hou at nxp.com>
>
> Fixup kernel DT to reserve memory for GIC redistributor tables,
> and initialize the redistributor configuration and pending
> tables using the reserved memory.
>
> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou at nxp.com>
> ---
>  board/freescale/ls2080aqds/ls2080aqds.c | 14 ++++++++++++++
>  board/freescale/ls2080ardb/ls2080ardb.c | 14 ++++++++++++++
>  2 files changed, 28 insertions(+)
>
> diff --git a/board/freescale/ls2080aqds/ls2080aqds.c b/board/freescale/ls2080aqds/ls2080aqds.c
> index 4034bdee28..fd63e6bc76 100644
> --- a/board/freescale/ls2080aqds/ls2080aqds.c
> +++ b/board/freescale/ls2080aqds/ls2080aqds.c
> @@ -3,6 +3,7 @@
>   * Copyright 2015 Freescale Semiconductor
>   */
>  #include <common.h>
> +#include <cpu_func.h>
>  #include <env.h>
>  #include <malloc.h>
>  #include <errno.h>
> @@ -12,6 +13,7 @@
>  #include <asm/io.h>
>  #include <fdt_support.h>
>  #include <linux/libfdt.h>
> +#include <linux/sizes.h>
>  #include <fsl-mc/fsl_mc.h>
>  #include <env_internal.h>
>  #include <i2c.h>
> @@ -21,12 +23,14 @@
>  #include <fsl_sec.h>
>  #include <asm/arch/ppa.h>
>  #include <asm/arch-fsl-layerscape/fsl_icid.h>
> +#include <asm/gic-v3.h>
>
>
>  #include "../common/qixis.h"
>  #include "ls2080aqds_qixis.h"
>  #include "../common/vid.h"
>
> +#define GIC_LPI_SIZE           0x200000
>  #define PIN_MUX_SEL_SDHC       0x00
>  #define PIN_MUX_SEL_DSPI       0x0a
>  #define SCFG_QSPICLKCTRL_DIV_20        (5 << 27)
> @@ -323,6 +327,8 @@ int ft_board_setup(void *blob, bd_t *bd)
>  {
>         u64 base[CONFIG_NR_DRAM_BANKS];
>         u64 size[CONFIG_NR_DRAM_BANKS];
> +       u64 gic_lpi_base;
> +       int ret;
>
>         ft_cpu_setup(blob, bd);
>
> @@ -333,6 +339,14 @@ int ft_board_setup(void *blob, bd_t *bd)
>         size[1] = gd->bd->bi_dram[1].size;
>
>  #ifdef CONFIG_RESV_RAM
> +#ifdef CONFIG_GIC_V3_ITS
> +       gic_lpi_base = ALIGN(gd->arch.resv_ram - GIC_LPI_SIZE, SZ_64K);
> +       ret = fdt_add_resv_mem_gic_rd_tables(blob, gic_lpi_base, GIC_LPI_SIZE);
> +       if (!ret) {
> +               if (gic_lpi_tables_init(gic_lpi_base, cpu_numcores()))
> +                       debug("%s: failed to init gic-lpi-tables\n", __func__);
> +       }

Is this board-specific fix-up, or LS2080 specific? If latter, we
should put it in the LS2080 SoC codes.

> +#endif
>         /* reduce size if reserved memory is within this bank */
>         if (gd->arch.resv_ram >= base[0] &&
>             gd->arch.resv_ram < base[0] + size[0])
> diff --git a/board/freescale/ls2080ardb/ls2080ardb.c b/board/freescale/ls2080ardb/ls2080ardb.c
> index 282aaf47fb..45e645f8de 100644
> --- a/board/freescale/ls2080ardb/ls2080ardb.c
> +++ b/board/freescale/ls2080ardb/ls2080ardb.c
> @@ -4,6 +4,7 @@
>   * Copyright 2017 NXP
>   */
>  #include <common.h>
> +#include <cpu_func.h>
>  #include <env.h>
>  #include <malloc.h>
>  #include <errno.h>
> @@ -14,6 +15,7 @@
>  #include <hwconfig.h>
>  #include <fdt_support.h>
>  #include <linux/libfdt.h>
> +#include <linux/sizes.h>
>  #include <fsl-mc/fsl_mc.h>
>  #include <env_internal.h>
>  #include <efi_loader.h>
> @@ -23,6 +25,7 @@
>  #include <asm/arch/ppa.h>
>  #include <fsl_sec.h>
>  #include <asm/arch-fsl-layerscape/fsl_icid.h>
> +#include <asm/gic-v3.h>
>
>  #ifdef CONFIG_FSL_QIXIS
>  #include "../common/qixis.h"
> @@ -30,6 +33,7 @@
>  #endif
>  #include "../common/vid.h"
>
> +#define GIC_LPI_SIZE           0x200000
>  #define PIN_MUX_SEL_SDHC       0x00
>  #define PIN_MUX_SEL_DSPI       0x0a
>
> @@ -421,6 +425,8 @@ int ft_board_setup(void *blob, bd_t *bd)
>         u64 mc_memory_base = 0;
>         u64 mc_memory_size = 0;
>         u16 total_memory_banks;
> +       u64 gic_lpi_base;
> +       int ret;
>
>         ft_cpu_setup(blob, bd);
>
> @@ -441,6 +447,14 @@ int ft_board_setup(void *blob, bd_t *bd)
>         size[1] = gd->bd->bi_dram[1].size;
>
>  #ifdef CONFIG_RESV_RAM
> +#ifdef CONFIG_GIC_V3_ITS
> +       gic_lpi_base = ALIGN(gd->arch.resv_ram - GIC_LPI_SIZE, SZ_64K);
> +       ret = fdt_add_resv_mem_gic_rd_tables(blob, gic_lpi_base, GIC_LPI_SIZE);
> +       if (!ret) {
> +               if (gic_lpi_tables_init(gic_lpi_base, cpu_numcores()))
> +                       debug("%s: failed to init gic-lpi-tables\n", __func__);
> +       }

ditto

> +#endif
>         /* reduce size if reserved memory is within this bank */
>         if (gd->arch.resv_ram >= base[0] &&
>             gd->arch.resv_ram < base[0] + size[0])
> --


Regards,
Bin
Zhiqiang Hou March 20, 2020, 7:35 a.m. UTC | #2 
Hi Bin,

Thanks a lot for your comments!

> -----Original Message-----
> From: Bin Meng <bmeng.cn at gmail.com>
> Sent: 2020?3?19? 19:57
> To: Z.q. Hou <zhiqiang.hou at nxp.com>
> Cc: U-Boot Mailing List <u-boot at lists.denx.de>; Priyanka Jain
> <priyanka.jain at nxp.com>
> Subject: Re: [PATCH 11/12] board: fsl: ls2080a: Initialize the GIC redistributor
> tables
> 
> On Thu, Mar 19, 2020 at 1:44 PM Zhiqiang Hou <Zhiqiang.Hou at nxp.com>
> wrote:
> >
> > From: Hou Zhiqiang <Zhiqiang.Hou at nxp.com>
> >
> > Fixup kernel DT to reserve memory for GIC redistributor tables, and
> > initialize the redistributor configuration and pending tables using
> > the reserved memory.
> >
> > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou at nxp.com>
> > ---
> >  board/freescale/ls2080aqds/ls2080aqds.c | 14 ++++++++++++++
> > board/freescale/ls2080ardb/ls2080ardb.c | 14 ++++++++++++++
> >  2 files changed, 28 insertions(+)
> >
> > diff --git a/board/freescale/ls2080aqds/ls2080aqds.c
> > b/board/freescale/ls2080aqds/ls2080aqds.c
> > index 4034bdee28..fd63e6bc76 100644
> > --- a/board/freescale/ls2080aqds/ls2080aqds.c
> > +++ b/board/freescale/ls2080aqds/ls2080aqds.c
> > @@ -3,6 +3,7 @@
> >   * Copyright 2015 Freescale Semiconductor
> >   */
> >  #include <common.h>
> > +#include <cpu_func.h>
> >  #include <env.h>
> >  #include <malloc.h>
> >  #include <errno.h>
> > @@ -12,6 +13,7 @@
> >  #include <asm/io.h>
> >  #include <fdt_support.h>
> >  #include <linux/libfdt.h>
> > +#include <linux/sizes.h>
> >  #include <fsl-mc/fsl_mc.h>
> >  #include <env_internal.h>
> >  #include <i2c.h>
> > @@ -21,12 +23,14 @@
> >  #include <fsl_sec.h>
> >  #include <asm/arch/ppa.h>
> >  #include <asm/arch-fsl-layerscape/fsl_icid.h>
> > +#include <asm/gic-v3.h>
> >
> >
> >  #include "../common/qixis.h"
> >  #include "ls2080aqds_qixis.h"
> >  #include "../common/vid.h"
> >
> > +#define GIC_LPI_SIZE           0x200000
> >  #define PIN_MUX_SEL_SDHC       0x00
> >  #define PIN_MUX_SEL_DSPI       0x0a
> >  #define SCFG_QSPICLKCTRL_DIV_20        (5 << 27)
> > @@ -323,6 +327,8 @@ int ft_board_setup(void *blob, bd_t *bd)  {
> >         u64 base[CONFIG_NR_DRAM_BANKS];
> >         u64 size[CONFIG_NR_DRAM_BANKS];
> > +       u64 gic_lpi_base;
> > +       int ret;
> >
> >         ft_cpu_setup(blob, bd);
> >
> > @@ -333,6 +339,14 @@ int ft_board_setup(void *blob, bd_t *bd)
> >         size[1] = gd->bd->bi_dram[1].size;
> >
> >  #ifdef CONFIG_RESV_RAM
> > +#ifdef CONFIG_GIC_V3_ITS
> > +       gic_lpi_base = ALIGN(gd->arch.resv_ram - GIC_LPI_SIZE,
> SZ_64K);
> > +       ret = fdt_add_resv_mem_gic_rd_tables(blob, gic_lpi_base,
> GIC_LPI_SIZE);
> > +       if (!ret) {
> > +               if (gic_lpi_tables_init(gic_lpi_base, cpu_numcores()))
> > +                       debug("%s: failed to init gic-lpi-tables\n",
> __func__);
> > +       }
> 
> Is this board-specific fix-up, or LS2080 specific? If latter, we should put it in
> the LS2080 SoC codes.

It's a SoC level fixup, I'll refine the series in v2.

Thanks,
Zhiqiang

> 
> > +#endif
> >         /* reduce size if reserved memory is within this bank */
> >         if (gd->arch.resv_ram >= base[0] &&
> >             gd->arch.resv_ram < base[0] + size[0]) diff --git
> > a/board/freescale/ls2080ardb/ls2080ardb.c
> > b/board/freescale/ls2080ardb/ls2080ardb.c
> > index 282aaf47fb..45e645f8de 100644
> > --- a/board/freescale/ls2080ardb/ls2080ardb.c
> > +++ b/board/freescale/ls2080ardb/ls2080ardb.c
> > @@ -4,6 +4,7 @@
> >   * Copyright 2017 NXP
> >   */
> >  #include <common.h>
> > +#include <cpu_func.h>
> >  #include <env.h>
> >  #include <malloc.h>
> >  #include <errno.h>
> > @@ -14,6 +15,7 @@
> >  #include <hwconfig.h>
> >  #include <fdt_support.h>
> >  #include <linux/libfdt.h>
> > +#include <linux/sizes.h>
> >  #include <fsl-mc/fsl_mc.h>
> >  #include <env_internal.h>
> >  #include <efi_loader.h>
> > @@ -23,6 +25,7 @@
> >  #include <asm/arch/ppa.h>
> >  #include <fsl_sec.h>
> >  #include <asm/arch-fsl-layerscape/fsl_icid.h>
> > +#include <asm/gic-v3.h>
> >
> >  #ifdef CONFIG_FSL_QIXIS
> >  #include "../common/qixis.h"
> > @@ -30,6 +33,7 @@
> >  #endif
> >  #include "../common/vid.h"
> >
> > +#define GIC_LPI_SIZE           0x200000
> >  #define PIN_MUX_SEL_SDHC       0x00
> >  #define PIN_MUX_SEL_DSPI       0x0a
> >
> > @@ -421,6 +425,8 @@ int ft_board_setup(void *blob, bd_t *bd)
> >         u64 mc_memory_base = 0;
> >         u64 mc_memory_size = 0;
> >         u16 total_memory_banks;
> > +       u64 gic_lpi_base;
> > +       int ret;
> >
> >         ft_cpu_setup(blob, bd);
> >
> > @@ -441,6 +447,14 @@ int ft_board_setup(void *blob, bd_t *bd)
> >         size[1] = gd->bd->bi_dram[1].size;
> >
> >  #ifdef CONFIG_RESV_RAM
> > +#ifdef CONFIG_GIC_V3_ITS
> > +       gic_lpi_base = ALIGN(gd->arch.resv_ram - GIC_LPI_SIZE,
> SZ_64K);
> > +       ret = fdt_add_resv_mem_gic_rd_tables(blob, gic_lpi_base,
> GIC_LPI_SIZE);
> > +       if (!ret) {
> > +               if (gic_lpi_tables_init(gic_lpi_base, cpu_numcores()))
> > +                       debug("%s: failed to init gic-lpi-tables\n",
> __func__);
> > +       }
> 
> ditto
> 
> > +#endif
> >         /* reduce size if reserved memory is within this bank */
> >         if (gd->arch.resv_ram >= base[0] &&
> >             gd->arch.resv_ram < base[0] + size[0])
> > --
> 
> 
> Regards,
> Bin
diff mbox series

Patch

diff --git a/board/freescale/ls2080aqds/ls2080aqds.c b/board/freescale/ls2080aqds/ls2080aqds.c
index 4034bdee28..fd63e6bc76 100644
--- a/board/freescale/ls2080aqds/ls2080aqds.c
+++ b/board/freescale/ls2080aqds/ls2080aqds.c
@@ -3,6 +3,7 @@ 
  * Copyright 2015 Freescale Semiconductor
  */
 #include <common.h>
+#include <cpu_func.h>
 #include <env.h>
 #include <malloc.h>
 #include <errno.h>
@@ -12,6 +13,7 @@ 
 #include <asm/io.h>
 #include <fdt_support.h>
 #include <linux/libfdt.h>
+#include <linux/sizes.h>
 #include <fsl-mc/fsl_mc.h>
 #include <env_internal.h>
 #include <i2c.h>
@@ -21,12 +23,14 @@ 
 #include <fsl_sec.h>
 #include <asm/arch/ppa.h>
 #include <asm/arch-fsl-layerscape/fsl_icid.h>
+#include <asm/gic-v3.h>
 
 
 #include "../common/qixis.h"
 #include "ls2080aqds_qixis.h"
 #include "../common/vid.h"
 
+#define GIC_LPI_SIZE		0x200000
 #define PIN_MUX_SEL_SDHC	0x00
 #define PIN_MUX_SEL_DSPI	0x0a
 #define SCFG_QSPICLKCTRL_DIV_20	(5 << 27)
@@ -323,6 +327,8 @@  int ft_board_setup(void *blob, bd_t *bd)
 {
 	u64 base[CONFIG_NR_DRAM_BANKS];
 	u64 size[CONFIG_NR_DRAM_BANKS];
+	u64 gic_lpi_base;
+	int ret;
 
 	ft_cpu_setup(blob, bd);
 
@@ -333,6 +339,14 @@  int ft_board_setup(void *blob, bd_t *bd)
 	size[1] = gd->bd->bi_dram[1].size;
 
 #ifdef CONFIG_RESV_RAM
+#ifdef CONFIG_GIC_V3_ITS
+	gic_lpi_base = ALIGN(gd->arch.resv_ram - GIC_LPI_SIZE, SZ_64K);
+	ret = fdt_add_resv_mem_gic_rd_tables(blob, gic_lpi_base, GIC_LPI_SIZE);
+	if (!ret) {
+		if (gic_lpi_tables_init(gic_lpi_base, cpu_numcores()))
+			debug("%s: failed to init gic-lpi-tables\n", __func__);
+	}
+#endif
 	/* reduce size if reserved memory is within this bank */
 	if (gd->arch.resv_ram >= base[0] &&
 	    gd->arch.resv_ram < base[0] + size[0])
diff --git a/board/freescale/ls2080ardb/ls2080ardb.c b/board/freescale/ls2080ardb/ls2080ardb.c
index 282aaf47fb..45e645f8de 100644
--- a/board/freescale/ls2080ardb/ls2080ardb.c
+++ b/board/freescale/ls2080ardb/ls2080ardb.c
@@ -4,6 +4,7 @@ 
  * Copyright 2017 NXP
  */
 #include <common.h>
+#include <cpu_func.h>
 #include <env.h>
 #include <malloc.h>
 #include <errno.h>
@@ -14,6 +15,7 @@ 
 #include <hwconfig.h>
 #include <fdt_support.h>
 #include <linux/libfdt.h>
+#include <linux/sizes.h>
 #include <fsl-mc/fsl_mc.h>
 #include <env_internal.h>
 #include <efi_loader.h>
@@ -23,6 +25,7 @@ 
 #include <asm/arch/ppa.h>
 #include <fsl_sec.h>
 #include <asm/arch-fsl-layerscape/fsl_icid.h>
+#include <asm/gic-v3.h>
 
 #ifdef CONFIG_FSL_QIXIS
 #include "../common/qixis.h"
@@ -30,6 +33,7 @@ 
 #endif
 #include "../common/vid.h"
 
+#define GIC_LPI_SIZE		0x200000
 #define PIN_MUX_SEL_SDHC	0x00
 #define PIN_MUX_SEL_DSPI	0x0a
 
@@ -421,6 +425,8 @@  int ft_board_setup(void *blob, bd_t *bd)
 	u64 mc_memory_base = 0;
 	u64 mc_memory_size = 0;
 	u16 total_memory_banks;
+	u64 gic_lpi_base;
+	int ret;
 
 	ft_cpu_setup(blob, bd);
 
@@ -441,6 +447,14 @@  int ft_board_setup(void *blob, bd_t *bd)
 	size[1] = gd->bd->bi_dram[1].size;
 
 #ifdef CONFIG_RESV_RAM
+#ifdef CONFIG_GIC_V3_ITS
+	gic_lpi_base = ALIGN(gd->arch.resv_ram - GIC_LPI_SIZE, SZ_64K);
+	ret = fdt_add_resv_mem_gic_rd_tables(blob, gic_lpi_base, GIC_LPI_SIZE);
+	if (!ret) {
+		if (gic_lpi_tables_init(gic_lpi_base, cpu_numcores()))
+			debug("%s: failed to init gic-lpi-tables\n", __func__);
+	}
+#endif
 	/* reduce size if reserved memory is within this bank */
 	if (gd->arch.resv_ram >= base[0] &&
 	    gd->arch.resv_ram < base[0] + size[0])