diff mbox series

[v1,04/10] mips: traps: Set WG bit in EBase register on Octeon

Message ID 20200502085944.13444-5-sr@denx.de
State New
Headers show
Series mips: Add initial Octeon MIPS64 base support | expand

Commit Message

Stefan Roese May 2, 2020, 8:59 a.m. UTC
WG (bit 11) needs to be set on Octeon to enable writing bits 63:30 of
the exception base register.

Signed-off-by: Stefan Roese <sr at denx.de>
---

 arch/mips/lib/traps.c | 4 ++++
 1 file changed, 4 insertions(+)

Comments

Daniel Schwierzeck May 13, 2020, 1:10 p.m. UTC | #1
Am 02.05.20 um 10:59 schrieb Stefan Roese:
> WG (bit 11) needs to be set on Octeon to enable writing bits 63:30 of
> the exception base register.
> 
> Signed-off-by: Stefan Roese <sr at denx.de>
> ---
> 
>  arch/mips/lib/traps.c | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/arch/mips/lib/traps.c b/arch/mips/lib/traps.c
> index 8fff7541e3..ccbce97161 100644
> --- a/arch/mips/lib/traps.c
> +++ b/arch/mips/lib/traps.c
> @@ -106,6 +106,10 @@ void trap_init(ulong reloc_addr)
>  
>  	saved_ebase = read_c0_ebase() & 0xfffff000;
>  
> +	/* Set WG bit on Octeon to enable writing to bits 63:30 */
> +	if (IS_ENABLED(CONFIG_ARCH_OCTEON))
> +		ebase |= BIT(11);

you should add something like this to mipsregs.h

#define EBASE_WG	(_ULCAST_(1)   << 11)

we already have EBASE_CPUNUM.

> +
>  	write_c0_ebase(ebase);
>  	clear_c0_status(ST0_BEV);
>  	execution_hazard_barrier();
>
Stefan Roese May 14, 2020, 8:21 a.m. UTC | #2
On 13.05.20 15:10, Daniel Schwierzeck wrote:
> 
> 
> Am 02.05.20 um 10:59 schrieb Stefan Roese:
>> WG (bit 11) needs to be set on Octeon to enable writing bits 63:30 of
>> the exception base register.
>>
>> Signed-off-by: Stefan Roese <sr at denx.de>
>> ---
>>
>>   arch/mips/lib/traps.c | 4 ++++
>>   1 file changed, 4 insertions(+)
>>
>> diff --git a/arch/mips/lib/traps.c b/arch/mips/lib/traps.c
>> index 8fff7541e3..ccbce97161 100644
>> --- a/arch/mips/lib/traps.c
>> +++ b/arch/mips/lib/traps.c
>> @@ -106,6 +106,10 @@ void trap_init(ulong reloc_addr)
>>   
>>   	saved_ebase = read_c0_ebase() & 0xfffff000;
>>   
>> +	/* Set WG bit on Octeon to enable writing to bits 63:30 */
>> +	if (IS_ENABLED(CONFIG_ARCH_OCTEON))
>> +		ebase |= BIT(11);
> 
> you should add something like this to mipsregs.h
> 
> #define EBASE_WG	(_ULCAST_(1)   << 11)
> 
> we already have EBASE_CPUNUM.

Sure, will do.

Thanks,
Stefan
diff mbox series

Patch

diff --git a/arch/mips/lib/traps.c b/arch/mips/lib/traps.c
index 8fff7541e3..ccbce97161 100644
--- a/arch/mips/lib/traps.c
+++ b/arch/mips/lib/traps.c
@@ -106,6 +106,10 @@  void trap_init(ulong reloc_addr)
 
 	saved_ebase = read_c0_ebase() & 0xfffff000;
 
+	/* Set WG bit on Octeon to enable writing to bits 63:30 */
+	if (IS_ENABLED(CONFIG_ARCH_OCTEON))
+		ebase |= BIT(11);
+
 	write_c0_ebase(ebase);
 	clear_c0_status(ST0_BEV);
 	execution_hazard_barrier();