diff mbox series

[09/13] dts: powerpc: p1010rdb: Add eTSEC DT nodes

Message ID 20200505113814.39047-10-Zhiqiang.Hou@nxp.com
State New
Headers show
Series powerpc: covert p1010, p1020 and p2020 RDB board | expand

Commit Message

Zhiqiang Hou May 5, 2020, 11:38 a.m. UTC 
From: Hou Zhiqiang <Zhiqiang.Hou at nxp.com>

P1010RDB implements 3 enhanced three-speed Ethernet controllers,
and the connection is shown below:
    eTSEC1: Connected to RGMII PHY AR8033
    eTSEC2: Connected to SGMII PHY AR8033
    eTSEC3: Connected to SGMII PHY AR8033

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou at nxp.com>
---
 arch/powerpc/dts/p1010rdb-pa.dts     |  1 +
 arch/powerpc/dts/p1010rdb-pa_36b.dts |  1 +
 arch/powerpc/dts/p1010rdb-pb.dts     |  1 +
 arch/powerpc/dts/p1010rdb-pb_36b.dts |  1 +
 arch/powerpc/dts/p1010rdb.dtsi       | 71 ++++++++++++++++++++++++++++
 arch/powerpc/dts/p1010si-post.dtsi   | 25 ++++++++++
 6 files changed, 100 insertions(+)
 create mode 100644 arch/powerpc/dts/p1010rdb.dtsi
diff mbox series

Patch

diff --git a/arch/powerpc/dts/p1010rdb-pa.dts b/arch/powerpc/dts/p1010rdb-pa.dts
index c66c4923ac..d46080d3ba 100644
--- a/arch/powerpc/dts/p1010rdb-pa.dts
+++ b/arch/powerpc/dts/p1010rdb-pa.dts
@@ -14,4 +14,5 @@ 
 	/include/ "p1010rdb_32b.dtsi"
 };
 
+/include/ "p1010rdb.dtsi"
 /include/ "p1010si-post.dtsi"
diff --git a/arch/powerpc/dts/p1010rdb-pa_36b.dts b/arch/powerpc/dts/p1010rdb-pa_36b.dts
index b943de7cbb..b9df5d46b2 100644
--- a/arch/powerpc/dts/p1010rdb-pa_36b.dts
+++ b/arch/powerpc/dts/p1010rdb-pa_36b.dts
@@ -14,4 +14,5 @@ 
 	/include/ "p1010rdb_36b.dtsi"
 };
 
+/include/ "p1010rdb.dtsi"
 /include/ "p1010si-post.dtsi"
diff --git a/arch/powerpc/dts/p1010rdb-pb.dts b/arch/powerpc/dts/p1010rdb-pb.dts
index 2675d5d92b..65deabd288 100644
--- a/arch/powerpc/dts/p1010rdb-pb.dts
+++ b/arch/powerpc/dts/p1010rdb-pb.dts
@@ -14,4 +14,5 @@ 
 	/include/ "p1010rdb_32b.dtsi"
 };
 
+/include/ "p1010rdb.dtsi"
 /include/ "p1010si-post.dtsi"
diff --git a/arch/powerpc/dts/p1010rdb-pb_36b.dts b/arch/powerpc/dts/p1010rdb-pb_36b.dts
index 45ccf91c41..1ba65a9f22 100644
--- a/arch/powerpc/dts/p1010rdb-pb_36b.dts
+++ b/arch/powerpc/dts/p1010rdb-pb_36b.dts
@@ -14,4 +14,5 @@ 
 	/include/ "p1010rdb_36b.dtsi"
 };
 
+/include/ "p1010rdb.dtsi"
 /include/ "p1010si-post.dtsi"
diff --git a/arch/powerpc/dts/p1010rdb.dtsi b/arch/powerpc/dts/p1010rdb.dtsi
new file mode 100644
index 0000000000..2040465bf4
--- /dev/null
+++ b/arch/powerpc/dts/p1010rdb.dtsi
@@ -0,0 +1,71 @@ 
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * P1010 RDB Device Tree Source stub (no addresses or top-level ranges)
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
+ */
+
+&soc {
+	mdio at 24000 {
+		phy0: ethernet-phy at 0 {
+			reg = <0x1>;
+		};
+
+		phy1: ethernet-phy at 1 {
+			reg = <0x0>;
+		};
+
+		phy2: ethernet-phy at 2 {
+			reg = <0x2>;
+		};
+
+		tbi-phy at 3 {
+			device_type = "tbi-phy";
+			reg = <0x3>;
+		};
+	};
+
+	mdio at 25000 {
+		tbi0: tbi-phy at 11 {
+			reg = <0x11>;
+			device_type = "tbi-phy";
+		};
+	};
+
+	mdio at 26000 {
+		tbi1: tbi-phy at 11 {
+			reg = <0x11>;
+			device_type = "tbi-phy";
+		};
+	};
+
+	ptp_clock at b0e00 {
+		compatible = "fsl,etsec-ptp";
+		reg = <0xb0e00 0xb0>;
+		interrupts = <68 2 0 0 69 2 0 0>;
+		fsl,tclk-period	= <10>;
+		fsl,tmr-prsc	= <2>;
+		fsl,tmr-add	= <0x80000016>;
+		fsl,tmr-fiper1	= <999999990>;
+		fsl,tmr-fiper2	= <99990>;
+		fsl,max-adj	= <199999999>;
+	};
+
+	enet0: ethernet at b0000 {
+		phy-handle = <&phy0>;
+		phy-connection-type = "rgmii-id";
+	};
+
+	enet1: ethernet at b1000 {
+		phy-handle = <&phy1>;
+		tbi-handle = <&tbi0>;
+		phy-connection-type = "sgmii";
+	};
+
+	enet2: ethernet at b2000 {
+		phy-handle = <&phy2>;
+		tbi-handle = <&tbi1>;
+		phy-connection-type = "sgmii";
+	};
+};
diff --git a/arch/powerpc/dts/p1010si-post.dtsi b/arch/powerpc/dts/p1010si-post.dtsi
index e24b5e4063..10de94a2e6 100644
--- a/arch/powerpc/dts/p1010si-post.dtsi
+++ b/arch/powerpc/dts/p1010si-post.dtsi
@@ -23,6 +23,31 @@ 
 		single-cpu-affinity;
 		last-interrupt-source = <255>;
 	};
+
+/include/ "pq3-etsec2-0.dtsi"
+	enet0: ethernet at b0000 {
+		queue-group at b0000 {
+			fsl,rx-bit-map = <0xff>;
+			fsl,tx-bit-map = <0xff>;
+		};
+	};
+
+/include/ "pq3-etsec2-1.dtsi"
+	enet1: ethernet at b1000 {
+		queue-group at b1000 {
+			fsl,rx-bit-map = <0xff>;
+			fsl,tx-bit-map = <0xff>;
+		};
+	};
+
+/include/ "pq3-etsec2-2.dtsi"
+	enet2: ethernet at b2000 {
+		queue-group at b2000 {
+			fsl,rx-bit-map = <0xff>;
+			fsl,tx-bit-map = <0xff>;
+		};
+
+	};
 };
 
 /* controller at 0x9000 */