| Message ID | 20200514095912.14428-5-sr@denx.de |
|---|---|
| State | Accepted |
| Commit | 1d4ba15c6fe1265c5964cce3436fd501b14bae3b |
| Headers | show |
| Series | mips: Add initial Octeon MIPS64 base support | expand |
diff --git a/arch/mips/lib/cache.c b/arch/mips/lib/cache.c index fdffe9493b..8dd025a79e 100644 --- a/arch/mips/lib/cache.c +++ b/arch/mips/lib/cache.c @@ -105,7 +105,7 @@ static inline unsigned long scache_line_size(void) } \ } while (0) -void flush_cache(ulong start_addr, ulong size) +void __weak flush_cache(ulong start_addr, ulong size) { unsigned long ilsize = icache_line_size(); unsigned long dlsize = dcache_line_size();
This patch adds __weak to flush_cache() in lib/cache.c. This makes it possible to overwrite this function by a platforms specific version, like done with the Octeon base port. Signed-off-by: Stefan Roese <sr at denx.de> --- Changes in v2: - New patch arch/mips/lib/cache.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)