diff mbox series

[v2,7/7] target/riscv: check before allocating TCG temps

Message ID 20200724002807.441147-8-richard.henderson@linaro.org
State New
Headers show
Series target/riscv: NaN-boxing for multiple precison | expand

Commit Message

Richard Henderson July 24, 2020, 12:28 a.m. UTC 
From: LIU Zhiwei <zhiwei_liu@c-sky.com>


Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>

Message-Id: <20200626205917.4545-5-zhiwei_liu@c-sky.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

---
 target/riscv/insn_trans/trans_rvd.inc.c | 8 ++++----
 target/riscv/insn_trans/trans_rvf.inc.c | 8 ++++----
 2 files changed, 8 insertions(+), 8 deletions(-)

-- 
2.25.1

Comments

Chih-Min Chao Aug. 6, 2020, 6:28 a.m. UTC | #1 
On Fri, Jul 24, 2020 at 8:32 AM Richard Henderson <
richard.henderson@linaro.org> wrote:

> From: LIU Zhiwei <zhiwei_liu@c-sky.com>

>

> Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>

> Message-Id: <20200626205917.4545-5-zhiwei_liu@c-sky.com>

> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

> ---

>  target/riscv/insn_trans/trans_rvd.inc.c | 8 ++++----

>  target/riscv/insn_trans/trans_rvf.inc.c | 8 ++++----

>  2 files changed, 8 insertions(+), 8 deletions(-)

>

> diff --git a/target/riscv/insn_trans/trans_rvd.inc.c

> b/target/riscv/insn_trans/trans_rvd.inc.c

> index ea1044f13b..4f832637fa 100644

> --- a/target/riscv/insn_trans/trans_rvd.inc.c

> +++ b/target/riscv/insn_trans/trans_rvd.inc.c

> @@ -20,10 +20,10 @@

>

>  static bool trans_fld(DisasContext *ctx, arg_fld *a)

>  {

> -    TCGv t0 = tcg_temp_new();

> -    gen_get_gpr(t0, a->rs1);

>      REQUIRE_FPU;

>      REQUIRE_EXT(ctx, RVD);

> +    TCGv t0 = tcg_temp_new();

> +    gen_get_gpr(t0, a->rs1);

>      tcg_gen_addi_tl(t0, t0, a->imm);

>

>      tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], t0, ctx->mem_idx, MO_TEQ);

> @@ -35,10 +35,10 @@ static bool trans_fld(DisasContext *ctx, arg_fld *a)

>

>  static bool trans_fsd(DisasContext *ctx, arg_fsd *a)

>  {

> -    TCGv t0 = tcg_temp_new();

> -    gen_get_gpr(t0, a->rs1);

>      REQUIRE_FPU;

>      REQUIRE_EXT(ctx, RVD);

> +    TCGv t0 = tcg_temp_new();

> +    gen_get_gpr(t0, a->rs1);

>      tcg_gen_addi_tl(t0, t0, a->imm);

>

>      tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], t0, ctx->mem_idx, MO_TEQ);

> diff --git a/target/riscv/insn_trans/trans_rvf.inc.c

> b/target/riscv/insn_trans/trans_rvf.inc.c

> index 0d04677a02..16df9c5ee2 100644

> --- a/target/riscv/insn_trans/trans_rvf.inc.c

> +++ b/target/riscv/insn_trans/trans_rvf.inc.c

> @@ -25,10 +25,10 @@

>

>  static bool trans_flw(DisasContext *ctx, arg_flw *a)

>  {

> -    TCGv t0 = tcg_temp_new();

> -    gen_get_gpr(t0, a->rs1);

>      REQUIRE_FPU;

>      REQUIRE_EXT(ctx, RVF);

> +    TCGv t0 = tcg_temp_new();

> +    gen_get_gpr(t0, a->rs1);

>      tcg_gen_addi_tl(t0, t0, a->imm);

>

>      tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], t0, ctx->mem_idx, MO_TEUL);

> @@ -41,11 +41,11 @@ static bool trans_flw(DisasContext *ctx, arg_flw *a)

>

>  static bool trans_fsw(DisasContext *ctx, arg_fsw *a)

>  {

> +    REQUIRE_FPU;

> +    REQUIRE_EXT(ctx, RVF);

>      TCGv t0 = tcg_temp_new();

>      gen_get_gpr(t0, a->rs1);

>

> -    REQUIRE_FPU;

> -    REQUIRE_EXT(ctx, RVF);

>      tcg_gen_addi_tl(t0, t0, a->imm);

>

>      tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], t0, ctx->mem_idx, MO_TEUL);

> --

> 2.25.1

>

>

>

Reviewed-by: Chih-Min Chao <chihmin.chao@sifive.com>


Chih-Min Chao
<div dir="ltr"><div dir="ltr"><div><div dir="ltr" class="gmail_signature" data-smartmail="gmail_signature"><div dir="ltr"><br></div></div></div></div><div class="gmail_quote"><div dir="ltr" class="gmail_attr">On Fri, Jul 24, 2020 at 8:32 AM Richard Henderson &lt;<a href="mailto:richard.henderson@linaro.org">richard.henderson@linaro.org</a>&gt; wrote:<br></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">From: LIU Zhiwei &lt;<a href="mailto:zhiwei_liu@c-sky.com" target="_blank">zhiwei_liu@c-sky.com</a>&gt;<br>
<br>
Signed-off-by: LIU Zhiwei &lt;<a href="mailto:zhiwei_liu@c-sky.com" target="_blank">zhiwei_liu@c-sky.com</a>&gt;<br>

Message-Id: &lt;<a href="mailto:20200626205917.4545-5-zhiwei_liu@c-sky.com" target="_blank">20200626205917.4545-5-zhiwei_liu@c-sky.com</a>&gt;<br>
Signed-off-by: Richard Henderson &lt;<a href="mailto:richard.henderson@linaro.org" target="_blank">richard.henderson@linaro.org</a>&gt;<br>

---<br>
 target/riscv/insn_trans/trans_rvd.inc.c | 8 ++++----<br>
 target/riscv/insn_trans/trans_rvf.inc.c | 8 ++++----<br>
 2 files changed, 8 insertions(+), 8 deletions(-)<br>
<br>
diff --git a/target/riscv/insn_trans/trans_rvd.inc.c b/target/riscv/insn_trans/trans_rvd.inc.c<br>
index ea1044f13b..4f832637fa 100644<br>
--- a/target/riscv/insn_trans/trans_rvd.inc.c<br>
+++ b/target/riscv/insn_trans/trans_rvd.inc.c<br>
@@ -20,10 +20,10 @@<br>
<br>
 static bool trans_fld(DisasContext *ctx, arg_fld *a)<br>
 {<br>
-    TCGv t0 = tcg_temp_new();<br>
-    gen_get_gpr(t0, a-&gt;rs1);<br>
     REQUIRE_FPU;<br>
     REQUIRE_EXT(ctx, RVD);<br>
+    TCGv t0 = tcg_temp_new();<br>
+    gen_get_gpr(t0, a-&gt;rs1);<br>
     tcg_gen_addi_tl(t0, t0, a-&gt;imm);<br>
<br>
     tcg_gen_qemu_ld_i64(cpu_fpr[a-&gt;rd], t0, ctx-&gt;mem_idx, MO_TEQ);<br>
@@ -35,10 +35,10 @@ static bool trans_fld(DisasContext *ctx, arg_fld *a)<br>
<br>
 static bool trans_fsd(DisasContext *ctx, arg_fsd *a)<br>
 {<br>
-    TCGv t0 = tcg_temp_new();<br>
-    gen_get_gpr(t0, a-&gt;rs1);<br>
     REQUIRE_FPU;<br>
     REQUIRE_EXT(ctx, RVD);<br>
+    TCGv t0 = tcg_temp_new();<br>
+    gen_get_gpr(t0, a-&gt;rs1);<br>
     tcg_gen_addi_tl(t0, t0, a-&gt;imm);<br>
<br>
     tcg_gen_qemu_st_i64(cpu_fpr[a-&gt;rs2], t0, ctx-&gt;mem_idx, MO_TEQ);<br>
diff --git a/target/riscv/insn_trans/trans_rvf.inc.c b/target/riscv/insn_trans/trans_rvf.inc.c<br>
index 0d04677a02..16df9c5ee2 100644<br>
--- a/target/riscv/insn_trans/trans_rvf.inc.c<br>
+++ b/target/riscv/insn_trans/trans_rvf.inc.c<br>
@@ -25,10 +25,10 @@<br>
<br>
 static bool trans_flw(DisasContext *ctx, arg_flw *a)<br>
 {<br>
-    TCGv t0 = tcg_temp_new();<br>
-    gen_get_gpr(t0, a-&gt;rs1);<br>
     REQUIRE_FPU;<br>
     REQUIRE_EXT(ctx, RVF);<br>
+    TCGv t0 = tcg_temp_new();<br>
+    gen_get_gpr(t0, a-&gt;rs1);<br>
     tcg_gen_addi_tl(t0, t0, a-&gt;imm);<br>
<br>
     tcg_gen_qemu_ld_i64(cpu_fpr[a-&gt;rd], t0, ctx-&gt;mem_idx, MO_TEUL);<br>
@@ -41,11 +41,11 @@ static bool trans_flw(DisasContext *ctx, arg_flw *a)<br>
<br>
 static bool trans_fsw(DisasContext *ctx, arg_fsw *a)<br>
 {<br>
+    REQUIRE_FPU;<br>
+    REQUIRE_EXT(ctx, RVF);<br>
     TCGv t0 = tcg_temp_new();<br>
     gen_get_gpr(t0, a-&gt;rs1);<br>
<br>
-    REQUIRE_FPU;<br>
-    REQUIRE_EXT(ctx, RVF);<br>
     tcg_gen_addi_tl(t0, t0, a-&gt;imm);<br>
<br>
     tcg_gen_qemu_st_i64(cpu_fpr[a-&gt;rs2], t0, ctx-&gt;mem_idx, MO_TEUL);<br>
-- <br>
2.25.1<br>
<br>
<br></blockquote><div><br></div><div>Reviewed-by: Chih-Min Chao &lt;<a href="mailto:chihmin.chao@sifive.com">chihmin.chao@sifive.com</a>&gt;</div><div><br></div><div><div dir="ltr" class="gmail_signature"><div dir="ltr"><span style="color:rgb(136,136,136)">Chih-Min Chao</span><div style="color:rgb(136,136,136)"></div></div></div></div><div> </div></div></div>
diff mbox series

Patch

diff --git a/target/riscv/insn_trans/trans_rvd.inc.c b/target/riscv/insn_trans/trans_rvd.inc.c
index ea1044f13b..4f832637fa 100644
--- a/target/riscv/insn_trans/trans_rvd.inc.c
+++ b/target/riscv/insn_trans/trans_rvd.inc.c
@@ -20,10 +20,10 @@ 
 
 static bool trans_fld(DisasContext *ctx, arg_fld *a)
 {
-    TCGv t0 = tcg_temp_new();
-    gen_get_gpr(t0, a->rs1);
     REQUIRE_FPU;
     REQUIRE_EXT(ctx, RVD);
+    TCGv t0 = tcg_temp_new();
+    gen_get_gpr(t0, a->rs1);
     tcg_gen_addi_tl(t0, t0, a->imm);
 
     tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], t0, ctx->mem_idx, MO_TEQ);
@@ -35,10 +35,10 @@  static bool trans_fld(DisasContext *ctx, arg_fld *a)
 
 static bool trans_fsd(DisasContext *ctx, arg_fsd *a)
 {
-    TCGv t0 = tcg_temp_new();
-    gen_get_gpr(t0, a->rs1);
     REQUIRE_FPU;
     REQUIRE_EXT(ctx, RVD);
+    TCGv t0 = tcg_temp_new();
+    gen_get_gpr(t0, a->rs1);
     tcg_gen_addi_tl(t0, t0, a->imm);
 
     tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], t0, ctx->mem_idx, MO_TEQ);
diff --git a/target/riscv/insn_trans/trans_rvf.inc.c b/target/riscv/insn_trans/trans_rvf.inc.c
index 0d04677a02..16df9c5ee2 100644
--- a/target/riscv/insn_trans/trans_rvf.inc.c
+++ b/target/riscv/insn_trans/trans_rvf.inc.c
@@ -25,10 +25,10 @@ 
 
 static bool trans_flw(DisasContext *ctx, arg_flw *a)
 {
-    TCGv t0 = tcg_temp_new();
-    gen_get_gpr(t0, a->rs1);
     REQUIRE_FPU;
     REQUIRE_EXT(ctx, RVF);
+    TCGv t0 = tcg_temp_new();
+    gen_get_gpr(t0, a->rs1);
     tcg_gen_addi_tl(t0, t0, a->imm);
 
     tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], t0, ctx->mem_idx, MO_TEUL);
@@ -41,11 +41,11 @@  static bool trans_flw(DisasContext *ctx, arg_flw *a)
 
 static bool trans_fsw(DisasContext *ctx, arg_fsw *a)
 {
+    REQUIRE_FPU;
+    REQUIRE_EXT(ctx, RVF);
     TCGv t0 = tcg_temp_new();
     gen_get_gpr(t0, a->rs1);
 
-    REQUIRE_FPU;
-    REQUIRE_EXT(ctx, RVF);
     tcg_gen_addi_tl(t0, t0, a->imm);
 
     tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], t0, ctx->mem_idx, MO_TEUL);