clk: samsung: Mark top BPLL mux on Exynos542x as critical

Message ID 20200805091601.11983-1-m.szyprowski@samsung.com
State New
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Series
  • clk: samsung: Mark top BPLL mux on Exynos542x as critical
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Commit Message

Marek Szyprowski Aug. 5, 2020, 9:16 a.m.
BPLL clock must not be disabled because it is needed for proper DRAM
operation. This is normally handled by respective memory devfreq driver,
but when that driver is not yet probed or its probe has been deferred the
clock might got disabled what causes board hang. Fix this by marking it
as critical.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>

---
 drivers/clk/samsung/clk-exynos5420.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

-- 
2.17.1

Comments

Lukasz Luba Aug. 5, 2020, 10:39 a.m. | #1
Hi Marek,

On 8/5/20 10:16 AM, Marek Szyprowski wrote:
> BPLL clock must not be disabled because it is needed for proper DRAM

> operation. This is normally handled by respective memory devfreq driver,

> but when that driver is not yet probed or its probe has been deferred the

> clock might got disabled what causes board hang. Fix this by marking it

> as critical.

> 

> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>

> ---

>   drivers/clk/samsung/clk-exynos5420.c | 2 +-

>   1 file changed, 1 insertion(+), 1 deletion(-)

> 

> diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c

> index fea33399a632..5ef78928938a 100644

> --- a/drivers/clk/samsung/clk-exynos5420.c

> +++ b/drivers/clk/samsung/clk-exynos5420.c

> @@ -734,7 +734,7 @@ static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = {

>   	MUX_F(CLK_MOUT_MCLK_CDREX, "mout_mclk_cdrex", mout_mclk_cdrex_p,

>   			SRC_CDREX, 4, 1, CLK_SET_RATE_PARENT, 0),

>   	MUX_F(CLK_MOUT_BPLL, "mout_bpll", mout_bpll_p, SRC_CDREX, 0, 1,

> -			CLK_SET_RATE_PARENT, 0),

> +			CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),

>   

>   	/* MAU Block */

>   	MUX(CLK_MOUT_MAUDIO0, "mout_maudio0", mout_maudio0_p, SRC_MAU, 28, 3),

> 


I've tested it in the way that we discussed yesterday.
I can confirm this patch solves the issue.

Reviewed-by: Lukasz Luba <lukasz.luba@arm.com>

Tested-by: Lukasz Luba <lukasz.luba@arm.com>


Thank you for investigating this further and fixing it.

Regards,
Lukasz
Krzysztof Kozlowski Aug. 5, 2020, 10:57 a.m. | #2
On Wed, Aug 05, 2020 at 11:16:01AM +0200, Marek Szyprowski wrote:
> BPLL clock must not be disabled because it is needed for proper DRAM

> operation. This is normally handled by respective memory devfreq driver,

> but when that driver is not yet probed or its probe has been deferred the

> clock might got disabled what causes board hang. Fix this by marking it

> as critical.

> 

> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>

> ---

>  drivers/clk/samsung/clk-exynos5420.c | 2 +-

>  1 file changed, 1 insertion(+), 1 deletion(-)


Acked-by: Krzysztof Kozlowski <krzk@kernel.org>


Best regards,
Krzysztof

Patch

diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index fea33399a632..5ef78928938a 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -734,7 +734,7 @@  static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = {
 	MUX_F(CLK_MOUT_MCLK_CDREX, "mout_mclk_cdrex", mout_mclk_cdrex_p,
 			SRC_CDREX, 4, 1, CLK_SET_RATE_PARENT, 0),
 	MUX_F(CLK_MOUT_BPLL, "mout_bpll", mout_bpll_p, SRC_CDREX, 0, 1,
-			CLK_SET_RATE_PARENT, 0),
+			CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
 
 	/* MAU Block */
 	MUX(CLK_MOUT_MAUDIO0, "mout_maudio0", mout_maudio0_p, SRC_MAU, 28, 3),