| Message ID | 1393087735-19261-4-git-send-email-omair.javaid@linaro.org |
|---|---|
| State | New |
| Headers | show |
On 22 February 2014 16:48, Omair Javaid <omair.javaid@linaro.org> wrote: > gdb: > > 2013-02-22 Omair Javaid <omair.javaid@linaro.org> > > * arm-tdep.c (arm_record_coproc_data_proc): Updated. > (arm_record_vfp_data_proc_insn): New function. > Changelog again, and comments below. > --- > gdb/arm-tdep.c | 221 +++++++++++++++++++++++++++++++++++++++++++++++++++++++-- > 1 file changed, 216 insertions(+), 5 deletions(-) > > diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c > index 76466c4..d0d9843 100644 > --- a/gdb/arm-tdep.c > +++ b/gdb/arm-tdep.c > @@ -11915,6 +11915,217 @@ arm_record_unsupported_insn (insn_decode_record *arm_insn_r) > return -1; > } > > +/* Record handler for arm/thumb mode VFP data processing instructions. */ > + > +static int > +arm_record_vfp_data_proc_insn (insn_decode_record *arm_insn_r) > +{ > + uint32_t opc1, opc2, opc3, dp_op_sz, bit_d, reg_vd; > + uint32_t record_buf[4]; > + uint8_t insn_type = -1; It might be clearer to make insn_type an enum. > + > + const int num_regs = gdbarch_num_regs (arm_insn_r->gdbarch); > + reg_vd = bits (arm_insn_r->arm_insn, 12, 15); > + opc1 = bits (arm_insn_r->arm_insn, 20, 23); > + opc2 = bits (arm_insn_r->arm_insn, 16, 19); > + opc3 = bits (arm_insn_r->arm_insn, 6, 7); > + dp_op_sz = bit (arm_insn_r->arm_insn, 8); > + bit_d = bit (arm_insn_r->arm_insn, 22); > + opc1 = opc1 & 0x04; > + > + /* Handle VMLA, VMLS. */ > + if (opc1 == 0x00) > + { > + if (bit (arm_insn_r->arm_insn, 10)) > + { > + if (bit (arm_insn_r->arm_insn, 6)) > + insn_type = 0; > + else > + insn_type = 1; > + } > + else > + { > + if (dp_op_sz) > + insn_type = 1; > + else > + insn_type = 2; > + } > + } > + /* Handle VNMLA, VNMLS, VNMUL. */ > + else if (opc1 == 0x01) > + { > + if (dp_op_sz) > + insn_type = 1; > + else > + insn_type = 2; > + } > + /* Handle VMUL. */ > + else if (opc1 == 0x02 && !(opc3 & 0x01)) > + { > + if (bit (arm_insn_r->arm_insn, 10)) > + { > + if (bit (arm_insn_r->arm_insn, 6)) > + insn_type = 0; > + else > + insn_type = 1; > + } > + else > + { > + if (dp_op_sz) > + insn_type = 1; > + else > + insn_type = 2; > + } > + } > + /* Handle VADD, VSUB. */ > + else if (opc1 == 0x03) > + { > + if (!bit (arm_insn_r->arm_insn, 9)) > + { > + if (bit (arm_insn_r->arm_insn, 6)) > + insn_type = 0; > + else > + insn_type = 1; > + } > + else > + { > + if (dp_op_sz) > + insn_type = 1; > + else > + insn_type = 2; > + } > + } > + /* Handle VDIV. */ > + else if (opc1 == 0x0b) > + { > + if (dp_op_sz) > + insn_type = 1; > + else > + insn_type = 2; > + } > + /* Handle all other vfp data processing instructions. */ > + else if (opc1 == 0x0b) > + { > + /* Handle VMOV. */ > + if (!(opc3 & 0x01) || (opc2 == 0x00 && opc3 == 0x01)) > + { > + if (bit (arm_insn_r->arm_insn, 4)) > + { > + if (bit (arm_insn_r->arm_insn, 6)) > + insn_type = 0; > + else > + insn_type = 1; > + } > + else > + { > + if (dp_op_sz) > + insn_type = 1; > + else > + insn_type = 2; > + } > + } > + /* Handle VNEG and VABS. */ > + else if ((opc2 == 0x01 && opc3 == 0x01) > + || (opc2 == 0x00 && opc3 == 0x03)) > + { > + if (!bit (arm_insn_r->arm_insn, 11)) > + { > + if (bit (arm_insn_r->arm_insn, 6)) > + insn_type = 0; > + else > + insn_type = 1; > + } > + else > + { > + if (dp_op_sz) > + insn_type = 1; > + else > + insn_type = 2; > + } > + } > + /* Handle VSQRT. */ > + else if (opc2 == 0x01 && opc3 == 0x03) > + { > + if (dp_op_sz) > + insn_type = 1; > + else > + insn_type = 2; > + } > + /* Handle VCVT. */ > + else if (opc2 == 0x07 && opc3 == 0x03) > + { > + if (!dp_op_sz) > + insn_type = 1; > + else > + insn_type = 2; > + } > + else if (opc3 & 0x01) > + { > + /* Handle VCVT. */ > + if ((opc2 == 0x08) || (opc2 & 0x0e) == 0x0c) > + { > + if (!bit (arm_insn_r->arm_insn, 18)) > + insn_type = 2; > + else > + { > + if (dp_op_sz) > + insn_type = 1; > + else > + insn_type = 2; > + } > + } > + /* Handle VCVT. */ > + else if ((opc2 & 0x0e) == 0x0a || (opc2 & 0x0e) == 0x0e) > + { > + if (dp_op_sz) > + insn_type = 1; > + else > + insn_type = 2; > + } > + /* Handle VCVTB, VCVTT. */ > + else if ((opc2 & 0x0e) == 0x02) > + insn_type = 2; > + /* Handle VCMP, VCMPE. */ > + else if ((opc2 & 0x0e) == 0x04) > + insn_type = 3; > + } > + } > + > + switch (insn_type) > + { > + case 0: > + reg_vd = reg_vd | (bit_d << 4); > + record_buf[0] = reg_vd + ARM_D0_REGNUM; > + record_buf[1] = reg_vd + ARM_D0_REGNUM + 1; > + arm_insn_r->reg_rec_count = 2; > + break; > + > + case 1: > + reg_vd = reg_vd | (bit_d << 4); > + record_buf[0] = reg_vd + ARM_D0_REGNUM; > + arm_insn_r->reg_rec_count = 1; > + break; > + > + case 2: > + reg_vd = (reg_vd << 1) | bit_d; > + record_buf[0] = reg_vd + num_regs; > + arm_insn_r->reg_rec_count = 1; > + break; > + > + case 3: > + record_buf[0] = ARM_FPSCR_REGNUM; > + arm_insn_r->reg_rec_count = 1; > + break; > + > + default: > + gdb_assert_not_reached ("no decoding pattern found"); > + break; > + } > + > + REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf); > + return 0; > +} > + > /* Handling opcode 110 insns. */ > > static int > @@ -12016,21 +12227,21 @@ arm_record_coproc_data_proc (insn_decode_record *arm_insn_r) > { > /* VFP data-processing instructions. */ > if (!op1_sbit && !op) > - return arm_record_unsupported_insn (arm_insn_r); > + return arm_record_vfp_data_proc_insn (arm_insn_r); > > /* Advanced SIMD, VFP instructions. */ > if (!op1_sbit && op) > - return arm_record_unsupported_insn (arm_insn_r); > + return arm_record_unsupported_insn(arm_insn_r); > } > else > { > /* Coprocessor data operations. */ > if (!op1_sbit && !op) > - return arm_record_unsupported_insn (arm_insn_r); > + return arm_record_unsupported_insn(arm_insn_r); > > /* Move to Coprocessor from ARM core register. */ > if (!op1_sbit && !op1_ebit && op) > - return arm_record_unsupported_insn (arm_insn_r); > + return arm_record_unsupported_insn(arm_insn_r); > > /* Move to arm core register from coprocessor. */ > if (!op1_sbit && op1_ebit && op) > @@ -12048,7 +12259,7 @@ arm_record_coproc_data_proc (insn_decode_record *arm_insn_r) > } > } > > - return arm_record_unsupported_insn (arm_insn_r); > + return arm_record_unsupported_insn(arm_insn_r); These changes should not be in the patch as they seem to be breaking the coding style. > } > > /* Handling opcode 000 insns. */ > -- > 1.8.3.2 >
On Wed 09 Apr 2014 03:28:53 PM PKT, Will Newton wrote: > On 22 February 2014 16:48, Omair Javaid <omair.javaid@linaro.org> wrote: >> gdb: >> >> 2013-02-22 Omair Javaid <omair.javaid@linaro.org> >> >> * arm-tdep.c (arm_record_coproc_data_proc): Updated. >> (arm_record_vfp_data_proc_insn): New function. >> > > Changelog again, and comments below. > >> --- >> gdb/arm-tdep.c | 221 +++++++++++++++++++++++++++++++++++++++++++++++++++++++-- >> 1 file changed, 216 insertions(+), 5 deletions(-) >> >> diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c >> index 76466c4..d0d9843 100644 >> --- a/gdb/arm-tdep.c >> +++ b/gdb/arm-tdep.c >> @@ -11915,6 +11915,217 @@ arm_record_unsupported_insn (insn_decode_record *arm_insn_r) >> return -1; >> } >> >> +/* Record handler for arm/thumb mode VFP data processing instructions. */ >> + >> +static int >> +arm_record_vfp_data_proc_insn (insn_decode_record *arm_insn_r) >> +{ >> + uint32_t opc1, opc2, opc3, dp_op_sz, bit_d, reg_vd; >> + uint32_t record_buf[4]; >> + uint8_t insn_type = -1; > > It might be clearer to make insn_type an enum. > >> + >> + const int num_regs = gdbarch_num_regs (arm_insn_r->gdbarch); >> + reg_vd = bits (arm_insn_r->arm_insn, 12, 15); >> + opc1 = bits (arm_insn_r->arm_insn, 20, 23); >> + opc2 = bits (arm_insn_r->arm_insn, 16, 19); >> + opc3 = bits (arm_insn_r->arm_insn, 6, 7); >> + dp_op_sz = bit (arm_insn_r->arm_insn, 8); >> + bit_d = bit (arm_insn_r->arm_insn, 22); >> + opc1 = opc1 & 0x04; >> + >> + /* Handle VMLA, VMLS. */ >> + if (opc1 == 0x00) >> + { >> + if (bit (arm_insn_r->arm_insn, 10)) >> + { >> + if (bit (arm_insn_r->arm_insn, 6)) >> + insn_type = 0; >> + else >> + insn_type = 1; >> + } >> + else >> + { >> + if (dp_op_sz) >> + insn_type = 1; >> + else >> + insn_type = 2; >> + } >> + } >> + /* Handle VNMLA, VNMLS, VNMUL. */ >> + else if (opc1 == 0x01) >> + { >> + if (dp_op_sz) >> + insn_type = 1; >> + else >> + insn_type = 2; >> + } >> + /* Handle VMUL. */ >> + else if (opc1 == 0x02 && !(opc3 & 0x01)) >> + { >> + if (bit (arm_insn_r->arm_insn, 10)) >> + { >> + if (bit (arm_insn_r->arm_insn, 6)) >> + insn_type = 0; >> + else >> + insn_type = 1; >> + } >> + else >> + { >> + if (dp_op_sz) >> + insn_type = 1; >> + else >> + insn_type = 2; >> + } >> + } >> + /* Handle VADD, VSUB. */ >> + else if (opc1 == 0x03) >> + { >> + if (!bit (arm_insn_r->arm_insn, 9)) >> + { >> + if (bit (arm_insn_r->arm_insn, 6)) >> + insn_type = 0; >> + else >> + insn_type = 1; >> + } >> + else >> + { >> + if (dp_op_sz) >> + insn_type = 1; >> + else >> + insn_type = 2; >> + } >> + } >> + /* Handle VDIV. */ >> + else if (opc1 == 0x0b) >> + { >> + if (dp_op_sz) >> + insn_type = 1; >> + else >> + insn_type = 2; >> + } >> + /* Handle all other vfp data processing instructions. */ >> + else if (opc1 == 0x0b) >> + { >> + /* Handle VMOV. */ >> + if (!(opc3 & 0x01) || (opc2 == 0x00 && opc3 == 0x01)) >> + { >> + if (bit (arm_insn_r->arm_insn, 4)) >> + { >> + if (bit (arm_insn_r->arm_insn, 6)) >> + insn_type = 0; >> + else >> + insn_type = 1; >> + } >> + else >> + { >> + if (dp_op_sz) >> + insn_type = 1; >> + else >> + insn_type = 2; >> + } >> + } >> + /* Handle VNEG and VABS. */ >> + else if ((opc2 == 0x01 && opc3 == 0x01) >> + || (opc2 == 0x00 && opc3 == 0x03)) >> + { >> + if (!bit (arm_insn_r->arm_insn, 11)) >> + { >> + if (bit (arm_insn_r->arm_insn, 6)) >> + insn_type = 0; >> + else >> + insn_type = 1; >> + } >> + else >> + { >> + if (dp_op_sz) >> + insn_type = 1; >> + else >> + insn_type = 2; >> + } >> + } >> + /* Handle VSQRT. */ >> + else if (opc2 == 0x01 && opc3 == 0x03) >> + { >> + if (dp_op_sz) >> + insn_type = 1; >> + else >> + insn_type = 2; >> + } >> + /* Handle VCVT. */ >> + else if (opc2 == 0x07 && opc3 == 0x03) >> + { >> + if (!dp_op_sz) >> + insn_type = 1; >> + else >> + insn_type = 2; >> + } >> + else if (opc3 & 0x01) >> + { >> + /* Handle VCVT. */ >> + if ((opc2 == 0x08) || (opc2 & 0x0e) == 0x0c) >> + { >> + if (!bit (arm_insn_r->arm_insn, 18)) >> + insn_type = 2; >> + else >> + { >> + if (dp_op_sz) >> + insn_type = 1; >> + else >> + insn_type = 2; >> + } >> + } >> + /* Handle VCVT. */ >> + else if ((opc2 & 0x0e) == 0x0a || (opc2 & 0x0e) == 0x0e) >> + { >> + if (dp_op_sz) >> + insn_type = 1; >> + else >> + insn_type = 2; >> + } >> + /* Handle VCVTB, VCVTT. */ >> + else if ((opc2 & 0x0e) == 0x02) >> + insn_type = 2; >> + /* Handle VCMP, VCMPE. */ >> + else if ((opc2 & 0x0e) == 0x04) >> + insn_type = 3; >> + } >> + } >> + >> + switch (insn_type) >> + { >> + case 0: >> + reg_vd = reg_vd | (bit_d << 4); >> + record_buf[0] = reg_vd + ARM_D0_REGNUM; >> + record_buf[1] = reg_vd + ARM_D0_REGNUM + 1; >> + arm_insn_r->reg_rec_count = 2; >> + break; >> + >> + case 1: >> + reg_vd = reg_vd | (bit_d << 4); >> + record_buf[0] = reg_vd + ARM_D0_REGNUM; >> + arm_insn_r->reg_rec_count = 1; >> + break; >> + >> + case 2: >> + reg_vd = (reg_vd << 1) | bit_d; >> + record_buf[0] = reg_vd + num_regs; >> + arm_insn_r->reg_rec_count = 1; >> + break; >> + >> + case 3: >> + record_buf[0] = ARM_FPSCR_REGNUM; >> + arm_insn_r->reg_rec_count = 1; >> + break; >> + >> + default: >> + gdb_assert_not_reached ("no decoding pattern found"); >> + break; >> + } >> + >> + REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf); >> + return 0; >> +} >> + >> /* Handling opcode 110 insns. */ >> >> static int >> @@ -12016,21 +12227,21 @@ arm_record_coproc_data_proc (insn_decode_record *arm_insn_r) >> { >> /* VFP data-processing instructions. */ >> if (!op1_sbit && !op) >> - return arm_record_unsupported_insn (arm_insn_r); >> + return arm_record_vfp_data_proc_insn (arm_insn_r); >> >> /* Advanced SIMD, VFP instructions. */ >> if (!op1_sbit && op) >> - return arm_record_unsupported_insn (arm_insn_r); >> + return arm_record_unsupported_insn(arm_insn_r); >> } >> else >> { >> /* Coprocessor data operations. */ >> if (!op1_sbit && !op) >> - return arm_record_unsupported_insn (arm_insn_r); >> + return arm_record_unsupported_insn(arm_insn_r); >> >> /* Move to Coprocessor from ARM core register. */ >> if (!op1_sbit && !op1_ebit && op) >> - return arm_record_unsupported_insn (arm_insn_r); >> + return arm_record_unsupported_insn(arm_insn_r); >> >> /* Move to arm core register from coprocessor. */ >> if (!op1_sbit && op1_ebit && op) >> @@ -12048,7 +12259,7 @@ arm_record_coproc_data_proc (insn_decode_record *arm_insn_r) >> } >> } >> >> - return arm_record_unsupported_insn (arm_insn_r); >> + return arm_record_unsupported_insn(arm_insn_r); > > These changes should not be in the patch as they seem to be breaking > the coding style. > >> } >> >> /* Handling opcode 000 insns. */ >> -- >> 1.8.3.2 >> > > > ping! Are there any further comments on this patch?
diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c index 76466c4..d0d9843 100644 --- a/gdb/arm-tdep.c +++ b/gdb/arm-tdep.c @@ -11915,6 +11915,217 @@ arm_record_unsupported_insn (insn_decode_record *arm_insn_r) return -1; } +/* Record handler for arm/thumb mode VFP data processing instructions. */ + +static int +arm_record_vfp_data_proc_insn (insn_decode_record *arm_insn_r) +{ + uint32_t opc1, opc2, opc3, dp_op_sz, bit_d, reg_vd; + uint32_t record_buf[4]; + uint8_t insn_type = -1; + + const int num_regs = gdbarch_num_regs (arm_insn_r->gdbarch); + reg_vd = bits (arm_insn_r->arm_insn, 12, 15); + opc1 = bits (arm_insn_r->arm_insn, 20, 23); + opc2 = bits (arm_insn_r->arm_insn, 16, 19); + opc3 = bits (arm_insn_r->arm_insn, 6, 7); + dp_op_sz = bit (arm_insn_r->arm_insn, 8); + bit_d = bit (arm_insn_r->arm_insn, 22); + opc1 = opc1 & 0x04; + + /* Handle VMLA, VMLS. */ + if (opc1 == 0x00) + { + if (bit (arm_insn_r->arm_insn, 10)) + { + if (bit (arm_insn_r->arm_insn, 6)) + insn_type = 0; + else + insn_type = 1; + } + else + { + if (dp_op_sz) + insn_type = 1; + else + insn_type = 2; + } + } + /* Handle VNMLA, VNMLS, VNMUL. */ + else if (opc1 == 0x01) + { + if (dp_op_sz) + insn_type = 1; + else + insn_type = 2; + } + /* Handle VMUL. */ + else if (opc1 == 0x02 && !(opc3 & 0x01)) + { + if (bit (arm_insn_r->arm_insn, 10)) + { + if (bit (arm_insn_r->arm_insn, 6)) + insn_type = 0; + else + insn_type = 1; + } + else + { + if (dp_op_sz) + insn_type = 1; + else + insn_type = 2; + } + } + /* Handle VADD, VSUB. */ + else if (opc1 == 0x03) + { + if (!bit (arm_insn_r->arm_insn, 9)) + { + if (bit (arm_insn_r->arm_insn, 6)) + insn_type = 0; + else + insn_type = 1; + } + else + { + if (dp_op_sz) + insn_type = 1; + else + insn_type = 2; + } + } + /* Handle VDIV. */ + else if (opc1 == 0x0b) + { + if (dp_op_sz) + insn_type = 1; + else + insn_type = 2; + } + /* Handle all other vfp data processing instructions. */ + else if (opc1 == 0x0b) + { + /* Handle VMOV. */ + if (!(opc3 & 0x01) || (opc2 == 0x00 && opc3 == 0x01)) + { + if (bit (arm_insn_r->arm_insn, 4)) + { + if (bit (arm_insn_r->arm_insn, 6)) + insn_type = 0; + else + insn_type = 1; + } + else + { + if (dp_op_sz) + insn_type = 1; + else + insn_type = 2; + } + } + /* Handle VNEG and VABS. */ + else if ((opc2 == 0x01 && opc3 == 0x01) + || (opc2 == 0x00 && opc3 == 0x03)) + { + if (!bit (arm_insn_r->arm_insn, 11)) + { + if (bit (arm_insn_r->arm_insn, 6)) + insn_type = 0; + else + insn_type = 1; + } + else + { + if (dp_op_sz) + insn_type = 1; + else + insn_type = 2; + } + } + /* Handle VSQRT. */ + else if (opc2 == 0x01 && opc3 == 0x03) + { + if (dp_op_sz) + insn_type = 1; + else + insn_type = 2; + } + /* Handle VCVT. */ + else if (opc2 == 0x07 && opc3 == 0x03) + { + if (!dp_op_sz) + insn_type = 1; + else + insn_type = 2; + } + else if (opc3 & 0x01) + { + /* Handle VCVT. */ + if ((opc2 == 0x08) || (opc2 & 0x0e) == 0x0c) + { + if (!bit (arm_insn_r->arm_insn, 18)) + insn_type = 2; + else + { + if (dp_op_sz) + insn_type = 1; + else + insn_type = 2; + } + } + /* Handle VCVT. */ + else if ((opc2 & 0x0e) == 0x0a || (opc2 & 0x0e) == 0x0e) + { + if (dp_op_sz) + insn_type = 1; + else + insn_type = 2; + } + /* Handle VCVTB, VCVTT. */ + else if ((opc2 & 0x0e) == 0x02) + insn_type = 2; + /* Handle VCMP, VCMPE. */ + else if ((opc2 & 0x0e) == 0x04) + insn_type = 3; + } + } + + switch (insn_type) + { + case 0: + reg_vd = reg_vd | (bit_d << 4); + record_buf[0] = reg_vd + ARM_D0_REGNUM; + record_buf[1] = reg_vd + ARM_D0_REGNUM + 1; + arm_insn_r->reg_rec_count = 2; + break; + + case 1: + reg_vd = reg_vd | (bit_d << 4); + record_buf[0] = reg_vd + ARM_D0_REGNUM; + arm_insn_r->reg_rec_count = 1; + break; + + case 2: + reg_vd = (reg_vd << 1) | bit_d; + record_buf[0] = reg_vd + num_regs; + arm_insn_r->reg_rec_count = 1; + break; + + case 3: + record_buf[0] = ARM_FPSCR_REGNUM; + arm_insn_r->reg_rec_count = 1; + break; + + default: + gdb_assert_not_reached ("no decoding pattern found"); + break; + } + + REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf); + return 0; +} + /* Handling opcode 110 insns. */ static int @@ -12016,21 +12227,21 @@ arm_record_coproc_data_proc (insn_decode_record *arm_insn_r) { /* VFP data-processing instructions. */ if (!op1_sbit && !op) - return arm_record_unsupported_insn (arm_insn_r); + return arm_record_vfp_data_proc_insn (arm_insn_r); /* Advanced SIMD, VFP instructions. */ if (!op1_sbit && op) - return arm_record_unsupported_insn (arm_insn_r); + return arm_record_unsupported_insn(arm_insn_r); } else { /* Coprocessor data operations. */ if (!op1_sbit && !op) - return arm_record_unsupported_insn (arm_insn_r); + return arm_record_unsupported_insn(arm_insn_r); /* Move to Coprocessor from ARM core register. */ if (!op1_sbit && !op1_ebit && op) - return arm_record_unsupported_insn (arm_insn_r); + return arm_record_unsupported_insn(arm_insn_r); /* Move to arm core register from coprocessor. */ if (!op1_sbit && op1_ebit && op) @@ -12048,7 +12259,7 @@ arm_record_coproc_data_proc (insn_decode_record *arm_insn_r) } } - return arm_record_unsupported_insn (arm_insn_r); + return arm_record_unsupported_insn(arm_insn_r); } /* Handling opcode 000 insns. */