From patchwork Sat Feb 22 16:48:54 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Omair Javaid X-Patchwork-Id: 25139 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-oa0-f71.google.com (mail-oa0-f71.google.com [209.85.219.71]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id CEDB9203C6 for ; Sat, 22 Feb 2014 16:49:36 +0000 (UTC) Received: by mail-oa0-f71.google.com with SMTP id g12sf22924074oah.6 for ; Sat, 22 Feb 2014 08:49:36 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:delivered-to:from:to:cc:subject :date:message-id:in-reply-to:references:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :list-post:list-help:list-archive:list-unsubscribe; bh=wyWMTHVxk8kPRI12gJD7W11Hj9YZsnWfm2ZBWm67w+A=; b=A0mfSoeXZy8HNhwCndQ8P0R81dnr/dLGizCgdqFA8TUy+fGZi0+9Zqv5XVAauC7FoU eksnAJXyw7lkPC0RdxeUweorRp9LIqTkM5krs2yuK9//mdAdSbvs5kn6hM9bWcD8x7ty QUerB5I/v7a/5KHKnyrsmdQlGk6fnTOU2KXhsAFM1nELF0YHfP0f/nbEHM373uKm9uCm o20qFp/E4ReMy8ZWU610xAGsFWDKH8vsvzFXlReySc3E6PKh/uC0N6dqdBRQl45kXtwZ z27BvhaIqCvG7HoYrR5K30Yv3wkOSfPTbaZICm69SS1KjTwMIlIRsT4DSpDuNirzvQgA 0/gQ== X-Gm-Message-State: ALoCoQkjzcBppcxH5dAkiFKyTj31qYseJUn4Zy4qTy9LQhTnXSD8gDsoIg5h8vunj+IbJYL96BgZ X-Received: by 10.182.74.226 with SMTP id x2mr5071339obv.1.1393087776232; Sat, 22 Feb 2014 08:49:36 -0800 (PST) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.140.30.8 with SMTP id c8ls1435845qgc.56.gmail; Sat, 22 Feb 2014 08:49:36 -0800 (PST) X-Received: by 10.52.89.230 with SMTP id br6mr7014306vdb.20.1393087776085; Sat, 22 Feb 2014 08:49:36 -0800 (PST) Received: from mail-ve0-f179.google.com (mail-ve0-f179.google.com [209.85.128.179]) by mx.google.com with ESMTPS id sx1si4262663vdc.62.2014.02.22.08.49.35 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Sat, 22 Feb 2014 08:49:36 -0800 (PST) Received-SPF: neutral (google.com: 209.85.128.179 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) client-ip=209.85.128.179; Received: by mail-ve0-f179.google.com with SMTP id jx11so4450772veb.10 for ; Sat, 22 Feb 2014 08:49:35 -0800 (PST) X-Received: by 10.52.189.98 with SMTP id gh2mr4259452vdc.86.1393087775847; Sat, 22 Feb 2014 08:49:35 -0800 (PST) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patches@linaro.org Received: by 10.220.174.196 with SMTP id u4csp114931vcz; Sat, 22 Feb 2014 08:49:35 -0800 (PST) X-Received: by 10.14.213.135 with SMTP id a7mr11412190eep.57.1393087774885; Sat, 22 Feb 2014 08:49:34 -0800 (PST) Received: from mail-ee0-f48.google.com (mail-ee0-f48.google.com [74.125.83.48]) by mx.google.com with ESMTPS id v48si23407925een.242.2014.02.22.08.49.34 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Sat, 22 Feb 2014 08:49:34 -0800 (PST) Received-SPF: neutral (google.com: 74.125.83.48 is neither permitted nor denied by best guess record for domain of omair.javaid@linaro.org) client-ip=74.125.83.48; Received: by mail-ee0-f48.google.com with SMTP id t10so2199918eei.21 for ; Sat, 22 Feb 2014 08:49:34 -0800 (PST) X-Received: by 10.14.2.193 with SMTP id 41mr14909653eef.55.1393087774450; Sat, 22 Feb 2014 08:49:34 -0800 (PST) Received: from localhost.localdomain ([175.110.189.84]) by mx.google.com with ESMTPSA id a2sm25596112eem.18.2014.02.22.08.49.29 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Sat, 22 Feb 2014 08:49:33 -0800 (PST) From: Omair Javaid To: gdb-patches@sourceware.org Cc: patches@linaro.org, Omair Javaid Subject: [PATCH 4/5] Support for recording extension register load/store instructions Date: Sat, 22 Feb 2014 21:48:54 +0500 Message-Id: <1393087735-19261-5-git-send-email-omair.javaid@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1393087735-19261-1-git-send-email-omair.javaid@linaro.org> References: <1393087735-19261-1-git-send-email-omair.javaid@linaro.org> X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: omair.javaid@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.128.179 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , gdb: 2013-02-22 Omair Javaid * arm-tdep.c (arm_record_asimd_vfp_coproc): Updated. (arm_record_exreg_ld_st_insn): New function. --- gdb/arm-tdep.c | 167 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 165 insertions(+), 2 deletions(-) diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c index d0d9843..a92e37a 100644 --- a/gdb/arm-tdep.c +++ b/gdb/arm-tdep.c @@ -11915,6 +11915,169 @@ arm_record_unsupported_insn (insn_decode_record *arm_insn_r) return -1; } +/* Record handler for extension register load/store instructions. */ + +static int +arm_record_exreg_ld_st_insn (insn_decode_record *arm_insn_r) +{ + uint32_t opcode, single_reg; + uint8_t op_vldm_vstm, op_vldr_vstr; + uint32_t record_buf[8], record_buf_mem[128]; + ULONGEST u_regval = 0; + + struct regcache *reg_cache = arm_insn_r->regcache; + const int num_regs = gdbarch_num_regs (arm_insn_r->gdbarch); + + opcode = bits (arm_insn_r->arm_insn, 20, 24); + single_reg = bit (arm_insn_r->arm_insn, 8); + op_vldm_vstm = opcode & 0x1b; + + /* Handle VMOV instructions. */ + if ((opcode & 0x1e) == 0x04) + { + if (bit (arm_insn_r->arm_insn, 4)) + { + record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); + record_buf[1] = bits (arm_insn_r->arm_insn, 16, 19); + arm_insn_r->reg_rec_count = 2; + } + else + { + uint8_t reg_m = (bits (arm_insn_r->arm_insn, 0, 3) << 1) + | bit (arm_insn_r->arm_insn, 5); + + if (!single_reg) + { + record_buf[0] = num_regs + reg_m; + record_buf[1] = num_regs + reg_m + 1; + arm_insn_r->reg_rec_count = 2; + } + else + { + record_buf[0] = reg_m + ARM_D0_REGNUM; + arm_insn_r->reg_rec_count = 1; + } + } + } + /* Handle VSTM and VPUSH instructions. */ + else if (op_vldm_vstm == 0x08 || op_vldm_vstm == 0x0a + || op_vldm_vstm == 0x12) + { + uint32_t start_address, reg_rn, imm_off32, imm_off8, memory_count; + uint32_t memory_index = 0; + + reg_rn = bits (arm_insn_r->arm_insn, 16, 19); + regcache_raw_read_unsigned (reg_cache, reg_rn, &u_regval); + imm_off8 = bits (arm_insn_r->arm_insn, 0, 7); + imm_off32 = imm_off8 << 24; + memory_count = imm_off8; + + if (bit (arm_insn_r->arm_insn, 23)) + start_address = u_regval; + else + start_address = u_regval - imm_off32; + + if (bit (arm_insn_r->arm_insn, 21)) + { + record_buf[0] = reg_rn; + arm_insn_r->reg_rec_count = 1; + } + + while (memory_count) + { + if (!single_reg) + { + record_buf_mem[memory_index] = start_address; + record_buf_mem[memory_index + 1] = 4; + start_address = start_address + 4; + memory_index = memory_index + 2; + } + else + { + record_buf_mem[memory_index] = start_address; + record_buf_mem[memory_index + 1] = 4; + record_buf_mem[memory_index + 2] = start_address + 4; + record_buf_mem[memory_index + 3] = 4; + start_address = start_address + 8; + memory_index = memory_index + 4; + } + memory_count--; + } + } + /* Handle VLDM instructions. */ + else if (op_vldm_vstm == 0x09 || op_vldm_vstm == 0x0b + || op_vldm_vstm == 0x13) + { + uint32_t reg_count, reg_vd; + uint32_t reg_index = 0; + + reg_vd = bits (arm_insn_r->arm_insn, 12, 15); + reg_count = bits (arm_insn_r->arm_insn, 0, 7); + + if (single_reg) + reg_vd = reg_vd | (bit (arm_insn_r->arm_insn, 0) << 4); + else + reg_vd = (reg_vd << 1) | bit (arm_insn_r->arm_insn, 0); + + if (bit (arm_insn_r->arm_insn, 21)) + record_buf[reg_index++] = bits (arm_insn_r->arm_insn, 16, 19); + + while (reg_count) + { + if (single_reg) + record_buf[reg_index++] = num_regs + reg_vd + reg_count - 1; + else + record_buf[reg_index++] = ARM_D0_REGNUM + reg_vd + reg_count - 1; + + reg_count--; + } + } + /* VSTR Vector store register. */ + else if ((opcode & 0x13) == 0x10) + { + uint32_t start_address, reg_rn, imm_off32, imm_off8, memory_count; + uint32_t memory_index = 0; + + reg_rn = bits (arm_insn_r->arm_insn, 16, 19); + regcache_raw_read_unsigned (reg_cache, reg_rn, &u_regval); + imm_off8 = bits (arm_insn_r->arm_insn, 0, 7); + imm_off32 = imm_off8 << 24; + memory_count = imm_off8; + + if (bit (arm_insn_r->arm_insn, 23)) + start_address = u_regval + imm_off32; + else + start_address = u_regval - imm_off32; + + if (single_reg) + { + record_buf_mem[memory_index] = start_address; + record_buf_mem[memory_index + 1] = 4; + } + else + { + record_buf_mem[memory_index] = start_address; + record_buf_mem[memory_index + 1] = 4; + record_buf_mem[memory_index + 2] = start_address + 4; + record_buf_mem[memory_index + 3] = 4; + } + } + /* VLDR Vector load register. */ + else if ((opcode & 0x13) == 0x11) + { + uint8_t single_reg = 0; + uint8_t special_case; + + record_buf[0] = 0; + record_buf[1] = 0; + arm_insn_r->reg_rec_count = 2; + } + + REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf); + MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem); + return 0; +} + /* Record handler for arm/thumb mode VFP data processing instructions. */ static int @@ -12143,11 +12306,11 @@ arm_record_asimd_vfp_coproc (insn_decode_record *arm_insn_r) { /* Handle extension register ld/st instructions. */ if (!(op1 & 0x20)) - return arm_record_unsupported_insn (arm_insn_r); + return arm_record_exreg_ld_st_insn (arm_insn_r); /* 64-bit transfers between arm core and extension registers. */ if ((op1 & 0x3e) == 0x04) - return arm_record_unsupported_insn (arm_insn_r); + return arm_record_exreg_ld_st_insn (arm_insn_r); } else {