[1/3] usb: dwc3: core: define bit 10 of GCTL register

Message ID 1393364180-15074-1-git-send-email-balbi@ti.com
State Accepted
Commit 183ca11179f6d3b99e0431bae6acb84350b82dea
Headers show

Commit Message

Felipe Balbi Feb. 25, 2014, 9:36 p.m.
This bit is necessary for implemeting workaround
for known issue with some revisions of this core.

Signed-off-by: Felipe Balbi <balbi@ti.com>
---
 drivers/usb/dwc3/core.h | 1 +
 1 file changed, 1 insertion(+)

Patch

diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index 5539cf1..00b0578 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -158,6 +158,7 @@ 
 #define DWC3_GCTL_PRTCAP_OTG	3
 
 #define DWC3_GCTL_CORESOFTRESET		(1 << 11)
+#define DWC3_GCTL_SOFITPSYNC		(1 << 10)
 #define DWC3_GCTL_SCALEDOWN(n)		((n) << 4)
 #define DWC3_GCTL_SCALEDOWN_MASK	DWC3_GCTL_SCALEDOWN(3)
 #define DWC3_GCTL_DISSCRAMBLE		(1 << 3)