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[50.57.142.19]) by mx.google.com with ESMTPS id eo2si466562qcb.53.2014.02.26.10.41.25 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Wed, 26 Feb 2014 10:41:26 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xen.org designates 50.57.142.19 as permitted sender) client-ip=50.57.142.19; Received: from localhost ([127.0.0.1] helo=lists.xen.org) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1WIjP9-0007zI-Vj; Wed, 26 Feb 2014 18:40:28 +0000 Received: from mail6.bemta5.messagelabs.com ([195.245.231.135]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1WIjOy-0007u4-Ui for xen-devel@lists.xensource.com; Wed, 26 Feb 2014 18:40:17 +0000 Received: from [85.158.139.211:33322] by server-6.bemta-5.messagelabs.com id 20/E4-14342-0153E035; Wed, 26 Feb 2014 18:40:16 +0000 X-Env-Sender: Stefano.Stabellini@citrix.com X-Msg-Ref: server-9.tower-206.messagelabs.com!1393440013!6451951!2 X-Originating-IP: [66.165.176.63] X-SpamReason: No, hits=0.0 required=7.0 tests=sa_preprocessor: VHJ1c3RlZCBJUDogNjYuMTY1LjE3Ni42MyA9PiAzMDYwNDg=\n X-StarScan-Received: X-StarScan-Version: 6.9.16; banners=-,-,- X-VirusChecked: Checked Received: (qmail 9470 invoked from network); 26 Feb 2014 18:40:15 -0000 Received: from smtp02.citrix.com (HELO SMTP02.CITRIX.COM) (66.165.176.63) by server-9.tower-206.messagelabs.com with RC4-SHA encrypted SMTP; 26 Feb 2014 18:40:15 -0000 X-IronPort-AV: E=Sophos;i="4.97,549,1389744000"; d="scan'208";a="104388728" Received: from accessns.citrite.net (HELO FTLPEX01CL03.citrite.net) ([10.9.154.239]) by FTLPIPO02.CITRIX.COM with ESMTP; 26 Feb 2014 18:40:12 +0000 Received: from ukmail1.uk.xensource.com (10.80.16.128) by smtprelay.citrix.com (10.13.107.80) with Microsoft SMTP Server id 14.2.342.4; Wed, 26 Feb 2014 13:40:10 -0500 Received: from kaball.uk.xensource.com ([10.80.2.59]) by ukmail1.uk.xensource.com with esmtp (Exim 4.69) (envelope-from ) id 1WIjOm-0004S3-B8; Wed, 26 Feb 2014 18:40:04 +0000 From: Stefano Stabellini To: Date: Wed, 26 Feb 2014 18:39:53 +0000 Message-ID: <1393439997-26936-8-git-send-email-stefano.stabellini@eu.citrix.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: References: MIME-Version: 1.0 X-DLP: MIA1 Cc: julien.grall@citrix.com, jtd@galois.com, Ian.Campbell@citrix.com, Stefano Stabellini Subject: [Xen-devel] [PATCH-4.5 v3 08/12] xen/arm: call gic_clear_lrs on entry to the hypervisor X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: List-Unsubscribe: , List-Post: , List-Help: , List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: stefano.stabellini@eu.citrix.com X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.220.180 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Archive: This change is needed by other patches later on. It is going to make sure that the calculation in Xen of the highest priority interrupt currently inflight is correct and accurate and not based on stale data. Signed-off-by: Stefano Stabellini --- xen/arch/arm/gic.c | 12 +++++------- xen/arch/arm/traps.c | 10 ++++++++++ xen/include/asm-arm/gic.h | 1 + 3 files changed, 16 insertions(+), 7 deletions(-) diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c index d1e7ed3..0e429c8 100644 --- a/xen/arch/arm/gic.c +++ b/xen/arch/arm/gic.c @@ -67,8 +67,6 @@ static DEFINE_PER_CPU(u8, gic_cpu_id); /* Maximum cpu interface per GIC */ #define NR_GIC_CPU_IF 8 -static void gic_clear_lrs(struct vcpu *v); - static unsigned int gic_cpu_mask(const cpumask_t *cpumask) { unsigned int cpu; @@ -130,7 +128,6 @@ void gic_restore_state(struct vcpu *v) GICH[GICH_HCR] = GICH_HCR_EN; isb(); - gic_clear_lrs(v); gic_restore_pending_irqs(v); } @@ -700,14 +697,15 @@ out: return; } -static void gic_clear_lrs(struct vcpu *v) +void gic_clear_lrs(struct vcpu *v) { struct pending_irq *p; int i = 0, irq; uint32_t lr; bool_t inflight; + unsigned long flags; - ASSERT(!local_irq_is_enabled()); + spin_lock_irqsave(&v->arch.vgic.lock, flags); while ((i = find_next_bit((const long unsigned int *) &this_cpu(lr_mask), nr_lrs, i)) < nr_lrs) { @@ -743,6 +741,8 @@ static void gic_clear_lrs(struct vcpu *v) i++; } + + spin_unlock_irqrestore(&v->arch.vgic.lock, flags); } static void gic_restore_pending_irqs(struct vcpu *v) @@ -785,8 +785,6 @@ int gic_events_need_delivery(void) void gic_inject(void) { - gic_clear_lrs(current); - if ( vcpu_info(current, evtchn_upcall_pending) ) vgic_vcpu_inject_irq(current, current->domain->arch.evtchn_irq); diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c index ea77cb8..7663114 100644 --- a/xen/arch/arm/traps.c +++ b/xen/arch/arm/traps.c @@ -70,6 +70,7 @@ static int debug_stack_lines = 40; integer_param("debug_stack_lines", debug_stack_lines); +static void enter_hypervisor_head(void); void __cpuinit init_traps(void) { @@ -1701,6 +1702,8 @@ asmlinkage void do_trap_hypervisor(struct cpu_user_regs *regs) { union hsr hsr = { .bits = READ_SYSREG32(ESR_EL2) }; + enter_hypervisor_head(); + switch (hsr.ec) { case HSR_EC_WFI_WFE: if ( !check_conditional_instr(regs, hsr) ) @@ -1778,11 +1781,13 @@ asmlinkage void do_trap_hypervisor(struct cpu_user_regs *regs) asmlinkage void do_trap_irq(struct cpu_user_regs *regs) { + enter_hypervisor_head(); gic_interrupt(regs, 0); } asmlinkage void do_trap_fiq(struct cpu_user_regs *regs) { + enter_hypervisor_head(); gic_interrupt(regs, 1); } @@ -1800,6 +1805,11 @@ asmlinkage void leave_hypervisor_tail(void) } } +static void enter_hypervisor_head(void) +{ + gic_clear_lrs(current); +} + /* * Local variables: * mode: C diff --git a/xen/include/asm-arm/gic.h b/xen/include/asm-arm/gic.h index 4834cd6..5a9dc77 100644 --- a/xen/include/asm-arm/gic.h +++ b/xen/include/asm-arm/gic.h @@ -220,6 +220,7 @@ extern unsigned int gic_number_lines(void); /* IRQ translation function for the device tree */ int gic_irq_xlate(const u32 *intspec, unsigned int intsize, unsigned int *out_hwirq, unsigned int *out_type); +void gic_clear_lrs(struct vcpu *v); #endif /* __ASSEMBLY__ */ #endif