From patchwork Sat Jul 9 17:16:36 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Shawn Guo X-Patchwork-Id: 2631 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 4742123F57 for ; Sat, 9 Jul 2011 17:05:47 +0000 (UTC) Received: from mail-qw0-f52.google.com (mail-qw0-f52.google.com [209.85.216.52]) by fiordland.canonical.com (Postfix) with ESMTP id 01C04A1857D for ; Sat, 9 Jul 2011 17:05:46 +0000 (UTC) Received: by qwb8 with SMTP id 8so1939581qwb.11 for ; Sat, 09 Jul 2011 10:05:46 -0700 (PDT) Received: by 10.229.1.140 with SMTP id 12mr2452738qcf.118.1310231146394; Sat, 09 Jul 2011 10:05:46 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.229.48.135 with SMTP id r7cs161018qcf; Sat, 9 Jul 2011 10:05:46 -0700 (PDT) Received: by 10.42.163.4 with SMTP id a4mr3532646icy.258.1310231145780; Sat, 09 Jul 2011 10:05:45 -0700 (PDT) Received: from mail-iy0-f178.google.com (mail-iy0-f178.google.com [209.85.210.178]) by mx.google.com with ESMTPS id m3si37424893icx.121.2011.07.09.10.05.44 (version=TLSv1/SSLv3 cipher=OTHER); Sat, 09 Jul 2011 10:05:44 -0700 (PDT) Received-SPF: neutral (google.com: 209.85.210.178 is neither permitted nor denied by best guess record for domain of shawn.guo@linaro.org) client-ip=209.85.210.178; Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.210.178 is neither permitted nor denied by best guess record for domain of shawn.guo@linaro.org) smtp.mail=shawn.guo@linaro.org Received: by iyb26 with SMTP id 26so3124825iyb.37 for ; Sat, 09 Jul 2011 10:05:44 -0700 (PDT) Received: by 10.231.179.208 with SMTP id br16mr2931517ibb.87.1310231144413; Sat, 09 Jul 2011 10:05:44 -0700 (PDT) Received: from localhost.localdomain ([114.216.146.213]) by mx.google.com with ESMTPS id y3sm1839319iba.4.2011.07.09.10.05.36 (version=TLSv1/SSLv3 cipher=OTHER); Sat, 09 Jul 2011 10:05:43 -0700 (PDT) From: Shawn Guo To: spi-devel-general@lists.sourceforge.net Cc: devicetree-discuss@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org, patches@linaro.org, Shawn Guo , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , Sascha Hauer , Grant Likely Subject: [PATCH v2 2/7] spi/imx: use mx21 to name SPI_IMX_VER_0_0 function and macro Date: Sun, 10 Jul 2011 01:16:36 +0800 Message-Id: <1310231801-18761-3-git-send-email-shawn.guo@linaro.org> X-Mailer: git-send-email 1.7.4.1 In-Reply-To: <1310231801-18761-1-git-send-email-shawn.guo@linaro.org> References: <1310231801-18761-1-git-send-email-shawn.guo@linaro.org> MIME-Version: 1.0 SPI_IMX_VER_0_0 covers i.mx21 and i.mx27. It makes more sense to use mx21 rather than mx27 to name SPI_IMX_VER_0_0 function and macro, since i.mx21 comes out ealier than i.mx27. Signed-off-by: Shawn Guo Cc: Uwe Kleine-König Cc: Sascha Hauer Cc: Grant Likely --- drivers/spi/spi-imx.c | 67 +++++++++++++++++++++++++------------------------ 1 files changed, 34 insertions(+), 33 deletions(-) diff --git a/drivers/spi/spi-imx.c b/drivers/spi/spi-imx.c index 1c55dc9..ad928b1 100644 --- a/drivers/spi/spi-imx.c +++ b/drivers/spi/spi-imx.c @@ -406,70 +406,71 @@ static void __maybe_unused spi_imx0_4_reset(struct spi_imx_data *spi_imx) readl(spi_imx->base + MXC_CSPIRXDATA); } -#define MX27_INTREG_RR (1 << 4) -#define MX27_INTREG_TEEN (1 << 9) -#define MX27_INTREG_RREN (1 << 13) - -#define MX27_CSPICTRL_POL (1 << 5) -#define MX27_CSPICTRL_PHA (1 << 6) -#define MX27_CSPICTRL_SSPOL (1 << 8) -#define MX27_CSPICTRL_XCH (1 << 9) -#define MX27_CSPICTRL_ENABLE (1 << 10) -#define MX27_CSPICTRL_MASTER (1 << 11) -#define MX27_CSPICTRL_DR_SHIFT 14 -#define MX27_CSPICTRL_CS_SHIFT 19 - -static void __maybe_unused mx27_intctrl(struct spi_imx_data *spi_imx, int enable) +#define MX21_INTREG_RR (1 << 4) +#define MX21_INTREG_TEEN (1 << 9) +#define MX21_INTREG_RREN (1 << 13) + +#define MX21_CSPICTRL_POL (1 << 5) +#define MX21_CSPICTRL_PHA (1 << 6) +#define MX21_CSPICTRL_SSPOL (1 << 8) +#define MX21_CSPICTRL_XCH (1 << 9) +#define MX21_CSPICTRL_ENABLE (1 << 10) +#define MX21_CSPICTRL_MASTER (1 << 11) +#define MX21_CSPICTRL_DR_SHIFT 14 +#define MX21_CSPICTRL_CS_SHIFT 19 + +static void __maybe_unused +mx21_intctrl(struct spi_imx_data *spi_imx, int enable) { unsigned int val = 0; if (enable & MXC_INT_TE) - val |= MX27_INTREG_TEEN; + val |= MX21_INTREG_TEEN; if (enable & MXC_INT_RR) - val |= MX27_INTREG_RREN; + val |= MX21_INTREG_RREN; writel(val, spi_imx->base + MXC_CSPIINT); } -static void __maybe_unused mx27_trigger(struct spi_imx_data *spi_imx) +static void __maybe_unused mx21_trigger(struct spi_imx_data *spi_imx) { unsigned int reg; reg = readl(spi_imx->base + MXC_CSPICTRL); - reg |= MX27_CSPICTRL_XCH; + reg |= MX21_CSPICTRL_XCH; writel(reg, spi_imx->base + MXC_CSPICTRL); } -static int __maybe_unused mx27_config(struct spi_imx_data *spi_imx, +static int __maybe_unused mx21_config(struct spi_imx_data *spi_imx, struct spi_imx_config *config) { - unsigned int reg = MX27_CSPICTRL_ENABLE | MX27_CSPICTRL_MASTER; + unsigned int reg = MX21_CSPICTRL_ENABLE | MX21_CSPICTRL_MASTER; int cs = spi_imx->chipselect[config->cs]; reg |= spi_imx_clkdiv_1(spi_imx->spi_clk, config->speed_hz) << - MX27_CSPICTRL_DR_SHIFT; + MX21_CSPICTRL_DR_SHIFT; reg |= config->bpw - 1; if (config->mode & SPI_CPHA) - reg |= MX27_CSPICTRL_PHA; + reg |= MX21_CSPICTRL_PHA; if (config->mode & SPI_CPOL) - reg |= MX27_CSPICTRL_POL; + reg |= MX21_CSPICTRL_POL; if (config->mode & SPI_CS_HIGH) - reg |= MX27_CSPICTRL_SSPOL; + reg |= MX21_CSPICTRL_SSPOL; if (cs < 0) - reg |= (cs + 32) << MX27_CSPICTRL_CS_SHIFT; + reg |= (cs + 32) << MX21_CSPICTRL_CS_SHIFT; writel(reg, spi_imx->base + MXC_CSPICTRL); return 0; } -static int __maybe_unused mx27_rx_available(struct spi_imx_data *spi_imx) +static int __maybe_unused mx21_rx_available(struct spi_imx_data *spi_imx) { - return readl(spi_imx->base + MXC_CSPIINT) & MX27_INTREG_RR; + return readl(spi_imx->base + MXC_CSPIINT) & MX21_INTREG_RR; } -static void __maybe_unused spi_imx0_0_reset(struct spi_imx_data *spi_imx) +static void __maybe_unused mx21_reset(struct spi_imx_data *spi_imx) { writel(1, spi_imx->base + MXC_RESET); } @@ -552,11 +553,11 @@ static struct spi_imx_devtype_data spi_imx_devtype_data[] = { #endif #ifdef CONFIG_SPI_IMX_VER_0_0 [SPI_IMX_VER_0_0] = { - .intctrl = mx27_intctrl, - .config = mx27_config, - .trigger = mx27_trigger, - .rx_available = mx27_rx_available, - .reset = spi_imx0_0_reset, + .intctrl = mx21_intctrl, + .config = mx21_config, + .trigger = mx21_trigger, + .rx_available = mx21_rx_available, + .reset = mx21_reset, .fifosize = 8, }, #endif