@@ -37,15 +37,14 @@ static inline void write_pte(lpae_t *p, lpae_t pte)
*/
static inline void flush_xen_text_tlb_local(void)
{
- register unsigned long r0 asm ("r0");
asm volatile (
"isb;" /* Ensure synchronization with previous changes to text */
- STORE_CP32(0, TLBIALLH) /* Flush hypervisor TLB */
- STORE_CP32(0, ICIALLU) /* Flush I-cache */
- STORE_CP32(0, BPIALL) /* Flush branch predictor */
+ CMD_CP32(TLBIALLH) /* Flush hypervisor TLB */
+ CMD_CP32(ICIALLU) /* Flush I-cache */
+ CMD_CP32(BPIALL) /* Flush branch predictor */
"dsb;" /* Ensure completion of TLB+BP flush */
"isb;"
- : : "r" (r0) /*dummy*/ : "memory");
+ : : : "memory");
}
/*
@@ -55,12 +54,11 @@ static inline void flush_xen_text_tlb_local(void)
*/
static inline void flush_xen_data_tlb_local(void)
{
- register unsigned long r0 asm ("r0");
asm volatile("dsb;" /* Ensure preceding are visible */
- STORE_CP32(0, TLBIALLH)
+ CMD_CP32(TLBIALLH)
"dsb;" /* Ensure completion of the TLB flush */
"isb;"
- : : "r" (r0) /* dummy */: "memory");
+ : : : "memory");
}
/*
@@ -69,6 +69,10 @@ struct cpu_user_regs
#define LOAD_CP64(r, name...) "mrrc " __stringify(CP64(%r, %H##r, name)) ";"
#define STORE_CP64(r, name...) "mcrr " __stringify(CP64(%r, %H##r, name)) ";"
+/* Issue a CP operation which takes no argument,
+ * uses r0 as a placeholder register. */
+#define CMD_CP32(name...) "mcr " __stringify(CP32(r0, name)) ";"
+
#ifndef __ASSEMBLY__
/* C wrappers */
TLBIALLH, ICIALLU and BPIALL make no use of their register argument. Instead of making the compiler allocate a dummy register just hardcode r0, there is no need to represent this in the inline asm since the register is neither clobbered nor used in any way. Signed-off-by: Ian Campbell <ian.campbell@citrix.com> --- xen/include/asm-arm/arm32/page.h | 14 ++++++-------- xen/include/asm-arm/arm32/processor.h | 4 ++++ 2 files changed, 10 insertions(+), 8 deletions(-)