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[v1,5/8] s390x/tcg: Implement BRANCH INDIRECT ON CONDITION (BIC)

Message ID 20200922103129.12824-6-david@redhat.com
State New
Headers show
Series s390x/tcg: Implement some z14 facilities | expand

Commit Message

David Hildenbrand Sept. 22, 2020, 10:31 a.m. UTC 
Just like BRANCH ON CONDITION - however the address is read from memory
(always 8 bytes are read), we have to wrap the address manually. The
address is read using current CPU DAT/address-space controls, just like
ordinary data.

Signed-off-by: David Hildenbrand <david@redhat.com>
---
 target/s390x/insn-data.def | 2 ++
 target/s390x/translate.c   | 5 +++++
 2 files changed, 7 insertions(+)

Comments

Richard Henderson Sept. 25, 2020, 9:45 p.m. UTC | #1 
On 9/22/20 3:31 AM, David Hildenbrand wrote:
> +/* BRANCH INDIRECT ON CONDITION */

> +    C(0xe347, BIC,     RXY_b, MIE2,0, m2_64, 0, 0, bc, 0)

>  /* BRANCH ON CONDITION */

>      C(0x0700, BCR,     RR_b,  Z,   0, r2_nz, 0, 0, bc, 0)

>      C(0x4700, BC,      RX_b,  Z,   0, a2, 0, 0, bc, 0)

> diff --git a/target/s390x/translate.c b/target/s390x/translate.c

> index b536491892..383edf7419 100644

> --- a/target/s390x/translate.c

> +++ b/target/s390x/translate.c

> @@ -1626,6 +1626,11 @@ static DisasJumpType op_bc(DisasContext *s, DisasOps *o)

>          return DISAS_NEXT;

>      }

>  

> +    /* For BIC the address came from memory, we need to wrap it again. */

> +    if (s->fields.op2 == 0x47) {

> +        gen_addi_and_wrap_i64(s, o->in2, o->in2, 0);

> +    }


I'm not keen on this sort of per-opcode checks.

I'd prefer to add an in2_m2_64w() helper that performs the load and then wraps.


r~
David Hildenbrand Sept. 28, 2020, 11:50 a.m. UTC | #2 
On 25.09.20 23:45, Richard Henderson wrote:
> On 9/22/20 3:31 AM, David Hildenbrand wrote:
>> +/* BRANCH INDIRECT ON CONDITION */
>> +    C(0xe347, BIC,     RXY_b, MIE2,0, m2_64, 0, 0, bc, 0)
>>  /* BRANCH ON CONDITION */
>>      C(0x0700, BCR,     RR_b,  Z,   0, r2_nz, 0, 0, bc, 0)
>>      C(0x4700, BC,      RX_b,  Z,   0, a2, 0, 0, bc, 0)
>> diff --git a/target/s390x/translate.c b/target/s390x/translate.c
>> index b536491892..383edf7419 100644
>> --- a/target/s390x/translate.c
>> +++ b/target/s390x/translate.c
>> @@ -1626,6 +1626,11 @@ static DisasJumpType op_bc(DisasContext *s, DisasOps *o)
>>          return DISAS_NEXT;
>>      }
>>  
>> +    /* For BIC the address came from memory, we need to wrap it again. */
>> +    if (s->fields.op2 == 0x47) {
>> +        gen_addi_and_wrap_i64(s, o->in2, o->in2, 0);
>> +    }
> 
> I'm not keen on this sort of per-opcode checks.
> 
> I'd prefer to add an in2_m2_64w() helper that performs the load and then wraps.

Makes sense, thanks!
diff mbox series

Patch

diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index 455efe73da..dfb0ec067b 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -115,6 +115,8 @@ 
 /* BRANCH RELATIVE AND SAVE */
     C(0xa705, BRAS,    RI_b,  Z,   0, 0, r1, 0, basi, 0)
     C(0xc005, BRASL,   RIL_b, Z,   0, 0, r1, 0, basi, 0)
+/* BRANCH INDIRECT ON CONDITION */
+    C(0xe347, BIC,     RXY_b, MIE2,0, m2_64, 0, 0, bc, 0)
 /* BRANCH ON CONDITION */
     C(0x0700, BCR,     RR_b,  Z,   0, r2_nz, 0, 0, bc, 0)
     C(0x4700, BC,      RX_b,  Z,   0, a2, 0, 0, bc, 0)
diff --git a/target/s390x/translate.c b/target/s390x/translate.c
index b536491892..383edf7419 100644
--- a/target/s390x/translate.c
+++ b/target/s390x/translate.c
@@ -1626,6 +1626,11 @@  static DisasJumpType op_bc(DisasContext *s, DisasOps *o)
         return DISAS_NEXT;
     }
 
+    /* For BIC the address came from memory, we need to wrap it again. */
+    if (s->fields.op2 == 0x47) {
+        gen_addi_and_wrap_i64(s, o->in2, o->in2, 0);
+    }
+
     disas_jcc(s, &c, m1);
     return help_branch(s, &c, is_imm, imm, o->in2);
 }