| Message ID | 1396445663-1357-2-git-send-email-haojian.zhuang@linaro.org |
|---|---|
| State | Accepted |
| Headers | show
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[2001:770:15f::2]) by mx.google.com with ESMTPS id ma8si866489wjb.226.2014.04.02.06.36.24 for <patch@linaro.org> (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 02 Apr 2014 06:36:25 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 2001:770:15f::2 as permitted sender) client-ip=2001:770:15f::2; Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1WVLK8-0001TK-Gh; Wed, 02 Apr 2014 13:35:24 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1WVLK2-0003wz-Go; Wed, 02 Apr 2014 13:35:18 +0000 Received: from mail-pa0-f51.google.com ([209.85.220.51]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1WVLK0-0003vF-2M for linux-arm-kernel@lists.infradead.org; Wed, 02 Apr 2014 13:35:16 +0000 Received: by mail-pa0-f51.google.com with SMTP id kq14so192404pab.24 for <linux-arm-kernel@lists.infradead.org>; Wed, 02 Apr 2014 06:34:52 -0700 (PDT) X-Received: by 10.68.143.231 with SMTP id sh7mr84274pbb.7.1396445692785; Wed, 02 Apr 2014 06:34:52 -0700 (PDT) Received: from localhost.localdomain ([140.206.182.114]) by mx.google.com with ESMTPSA id ac5sm4560323pbc.37.2014.04.02.06.34.44 for <multiple recipients> (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 02 Apr 2014 06:34:52 -0700 (PDT) From: Haojian Zhuang <haojian.zhuang@linaro.org> To: linux@arm.linux.org.uk, linux-arm-kernel@lists.infradead.org, arnd@arndb.de, olof@lixom.net, khilman@kernel.org, xuwei5@hisilicon.com Subject: [PATCH 2/2] ARM: dts: fix L2 address in Hi3620 Date: Wed, 2 Apr 2014 21:34:23 +0800 Message-Id: <1396445663-1357-2-git-send-email-haojian.zhuang@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1396445663-1357-1-git-send-email-haojian.zhuang@linaro.org> References: <1396445663-1357-1-git-send-email-haojian.zhuang@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140402_093516_226525_77EF5EC4 X-CRM114-Status: GOOD ( 10.34 ) X-Spam-Score: -2.6 (--) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-2.6 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [209.85.220.51 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: Haojian Zhuang <haojian.zhuang@linaro.org> X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: <patchwork-forward.linaro.org> List-Unsubscribe: <http://groups.google.com/a/linaro.org/group/patchwork-forward/subscribe>, <mailto:googlegroups-manage+836684582541+unsubscribe@googlegroups.com> List-Archive: <http://groups.google.com/a/linaro.org/group/patchwork-forward/> List-Post: <http://groups.google.com/a/linaro.org/group/patchwork-forward/post>, <mailto:patchwork-forward@linaro.org> List-Help: <http://support.google.com/a/linaro.org/bin/topic.py?topic=25838>, <mailto:patchwork-forward+help@linaro.org> List-Subscribe: <http://lists.infradead.org/mailman/listinfo/linux-arm-kernel>, <mailto:linux-arm-kernel-request@lists.infradead.org?subject=subscribe> MIME-Version: 1.0 Sender: "linux-arm-kernel" <linux-arm-kernel-bounces@lists.infradead.org> Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org X-Removed-Original-Auth: Dkim didn't pass. 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diff --git a/arch/arm/boot/dts/hi3620.dtsi b/arch/arm/boot/dts/hi3620.dtsi index ab1116d..83a5b86 100644 --- a/arch/arm/boot/dts/hi3620.dtsi +++ b/arch/arm/boot/dts/hi3620.dtsi @@ -73,7 +73,7 @@ L2: l2-cache { compatible = "arm,pl310-cache"; - reg = <0xfc10000 0x100000>; + reg = <0x100000 0x100000>; interrupts = <0 15 4>; cache-unified; cache-level = <2>;
Fix the address of L2 controler register in hi3620 SoC. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org> --- arch/arm/boot/dts/hi3620.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)