diff mbox series

[2/3] target/riscv: Fix write_htinst() implementation

Message ID 20200729112801.108985-3-anup.patel@wdc.com
State New
Headers show
Series [1/3] target/riscv: Optional feature to provide trapped instruction in CSRs | expand

Commit Message

Anup Patel July 29, 2020, 11:28 a.m. UTC 
The htinst CSR is writeable from M-mode and HS-mode so
we should not ignore writes to htinst CSR.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
---
 target/riscv/csr.c | 1 +
 1 file changed, 1 insertion(+)
diff mbox series

Patch

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index f985b85de4..99fcb7f67d 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -943,6 +943,7 @@  static int read_htinst(CPURISCVState *env, int csrno, target_ulong *val)
 
 static int write_htinst(CPURISCVState *env, int csrno, target_ulong val)
 {
+    env->htinst = val;
     return 0;
 }